Trigger for the SoLid Reactor Antineutrino Experiment

TL;DR

The paper presents a trigger system for the SoLid reactor antineutrino experiment, using FPGA-based algorithms to distinguish signal from background noise in real-time, enabling precise neutrino measurements at a short baseline.

Contribution

It introduces a novel FPGA firmware trigger with peak counting and time-over-threshold algorithms for real-time background rejection in the SoLid experiment.

Findings

Effective FPGA trigger algorithms identified and implemented.

High efficiency and low fake rate demonstrated.

Enhanced signal-background discrimination for neutrino detection.

Abstract

SoLid, located at SCK-CEN in Mol, Belgium, is a reactor antineutrino experiment at a very short baseline of 5.5 -- 10m aiming at the search for sterile neutrinos and for high precision measurement of the neutrino energy spectrum of Uranium-235. It uses a novel approach using Lithium-6 sheets and PVT cubes as scintillators for tagging the Inverse Beta-Decay products (neutron and positron). Being located overground and close to the BR2 research reactor, the experiment faces a large amount of backgrounds. Efficient real-time background and noise rejection is essential in order to increase the signal-background ratio for precise oscillation measurement and decrease data production to a rate which can be handled by the online software. Therefore, a reliable distinction between the neutrons and background signals is crucial. This can be performed online with a dedicated firmware trigger. A peak counting algorithm and an algorithm measuring time over threshold have been identified as performing well both in terms of efficiency and fake rate, and have been implemented onto FPGA.