RaPro: A Novel 5G Rapid Prototyping System Architecture

TL;DR

This paper introduces RaPro, a flexible and scalable 5G prototyping system architecture that combines FPGA modules with high-level programming for advanced algorithms, demonstrated through a multi-user MIMO system.

Contribution

It presents a novel 5G prototyping architecture integrating FPGA modules with high-level programming, enhancing flexibility and scalability.

Findings

Demonstrated superior performance in large-scale antenna systems

Achieved effective multi-user MIMO communication

Validated architecture's scalability and flexibility

Abstract

We propose a novel fifth-generation (5G) rapid prototyping (RaPro) system architecture by combining FPGA-privileged modules from a software defined radio (or FPGA-coprocessor) and high-level programming language for advanced algorithms from multi-core general purpose processors. The proposed system architecture exhibits excellent flexibility and scalability in the development of a 5G prototyping system. As a proof of concept, a multi-user full-dimension multiple-input and multiple-output system is established based on the proposed architecture. Experimental results demonstrate the superiority of the proposed architecture in large-scale antenna and wideband communication systems.

Tables

Table 1. TABLE I: CPU load analysis for subframe processing CPU cores under different settings.

Settings	Module (CPU cycles)			Total cycles	Time	Duty cycle(T)
(20MHz)	${𝐇}_{\mathrm{𝐞𝐬𝐭}}$	Detector	Others	(Per core)	@2.8GHz	(Per core)
16x4	66k	3800k	940k	4806k	1.716ms	17.16%
16x12	188k	5000k	1340k	6128k	2.189ms	21.89%
128x12	1504k	15240k	6520k	23264k	8.309ms	83.09%

Table 2. TABLE II: Comparison among existing prototyping systems.

o 0.68X[2.5,c] X[2,c] X[2,c] X[c] X[2,c] X[1.5,c] X[2,c]	# of BS antennas	Bandwidth	FFT Size	Hardware	Develop. period	Scalability/ Flexibility
RaPro	up to 128	20MHz	2048	GPP+FPGA	Short	High/High
[11]	128	20MHz	2048	FPGA	Long	High/Low
Argos	up to 96	625KHz	-	FPGA	Long	Med./Low
LuMaMi	100	20MHz	2048	FPGA	Long	High/Low
BigStation	12	20MHz	64	GPP+Sora	Short	Low/High
OAI testbed	up to 64	5MHz	512	OAI+FPGA	Short	Med./Med.

Full text

I Introduction

With emerging applications and services from wireless networks, the volume of mobile traffic and the number of devices have exponentially increased. To accommodate these demands, researchers proposed several promising technologies, such as massive multiple-input multiple-output (MIMO), millimeter wave (mmWave), and ultra-densification, for the development of fifth-generation (5G) or next generation wireless communication systems. These technologies have been used to address demands through different dimensions, such as spectrum efficiency enhancement, spectrum extension, and network densification [1].

To verify the anticipated gain from large-scale antenna array, researchers established several basic massive MIMO prototyping systems. Based on their signal processing realization methods, the prototyping systems can be roughly classified into two categories, namely, FPGA-based prototyping system and general purpose processor(GPP)-based prototyping system. FPGA-based prototyping systems include Argos [2, 3, 4] developed by Rice University and LuMaMi [5] created by Lund University. Some examples of GPP-based prototyping systems are Open Air Interface (OAI) massive MIMO testbed [6, 7] developed by Eurecom team, and BigStation [8] developed by Microsoft Research team with the Microsoft Research Software Radio (Sora) [9]. However, FPGA-based prototyping systems constantly suffer from long programming and compile time, whereas the performance of OAI and Sora are constrained by their specialized hardware driver and software stack.

To address these limitations, we propose a novel system architecture by extracting the advantages of the software-defined radio (SDR) platforms and multi-core GPPs through a high-speed 10-Gigabit (G) Ethernet interface connection. In particular, we distribute FPGA-privileged modules into SDRs, such as FFT/IFFT; implement complex innovative algorithms, such as advanced receiver algorithms, in multi-core GPPs using high-level language; and connect SDRs and GPPs with 10-Gigabit Ethernet interfaces. The proposed system architecture is flexible and scalable in terms of the number of antennas and transmission bandwidth, and can be applied to various scenarios, such as full-dimension MIMO, centralized/distributed massive MIMO, mmWave, and cloud-based networking.

II System Architecture

In this section, the proposed system architecture is briefly introduced, and the application scenarios are presented.

II-A Overview

Fig. 1 illustrates the proposed system architecture, which comprises SDRs, FPGA-coprocessors, timing/synchronization modules, high-speed 10G Ethernet switches, and multi-core GPPs. Compared with the conventional prototyping system architectures, our proposed system architecture introduces an FPGA-coprocessor and a high-speed Ethernet interface to enhance the capability of real-time signal processing and data transfer between SDRs and GPPs.

SDRs contain RF chains provided with a unified reference clock and trigger signal by the timing/synchronization module in each subsystem. Data reordering and bandwidth splitting based on the antenna or subcarrier index are conducted in FPGA-coprocessors, which are assembled in a peripheral component interconnect eXtensions for instrumentation (PXI) chassis per subsystem. User datagram protocol (UDP)-packets and latency-constrained signal processing modules are implemented in the FPGA-coprocessors. High-speed switches aggregate or distribute data between subsystems and multi-core GPPs. Advanced baseband algorithms are obtained in multi-core GPPs through multiple parallel threads with high-level language in a Linux environment.

The proposed architecture offers the following advantages:

• •

Scalability and flexibility. The proposed system architecture is highly scalable in terms of the number of antennas and transmission bandwidth with the introduction of other subsystems, more subband (subframe) division, and other powerful multi-core GPPs, owing to the utilization of a subsystem and baseband data partition in a frequency (e.g., subband) or time (e.g., subframe) domain inside FPGA-coprocessors111The data transmission rate and peer-to-peer link pipes between FPGA-coprocessors are hardware-constrained.. The system can also be conveniently configured as either centralized or distributed using multimode fibers for 10G Ethernet ports. Moreover, innovative algorithms can be deployed flexibly on either FPGA-coprocessors or GPPs.

• •

High computational capability. The proposed architecture exhibits low-processing latency and high computation capability with the stack of FPGA-coprocessors and advanced GPPs. This is because multiple parallel threads are used in multi-core GPPs, in which each thread is allocated to an individual core (running at 2.8 GHz versus 200 MHz in FPGA-coprocessors), and each core is obliged to finish small detailed tasks in a parallel or pipeline manner.

• •

Rapid and easy development. Innovative algorithms and large dimension matrix computation can be developed on multi-core GPPs by programming with high-level language, such as C/C++, in conjunction with Intel Math Kernel Library (Intel MKL) [10], which is a highly optimized and commonly used math library for processors. Algorithm development with this approach is much more rapid and convenient than with Verilog for FPGAs in conventional prototyping systems.

II-B Application Scenarios

The proposed system architecture can be used for various scenarios, such as full-dimension MIMO, centralized/distributed massive MIMO, mmWave, and cloud-based networking.

Centralized/distributed massive MIMO: Excluding the 10G Ethernet connection and multi-core GPPs, our earlier work [11] revealed a 128-antenna massive MIMO prototyping system similar to the proposed system architecture in Fig. 1. Therefore, the proposed system architecture is made feasible by only verifying the data transmission rate from FPGA-coprocessors to multi-core GPPs and the real-time computation capability in multi-core GPPs, as demonstrated in Section III.

mmWave: Wide bandwidth, high sample rate, and high data throughput are among the main challenges in prototyping an mmWave system. An mmWave prototyping system can be established based on the usage of data partition in frequency or time domain in FPGA-coprocessors with the aid of more high-speed Ethernet switches and more advanced multi-core GPPs, in which each GPP is responsible for subband (or subframe) data processing.

Cloud-based network: A prototyping system based on the proposed system architecture can inherently exchange data with an external network using a UDP packet and an Ethernet interface. Therefore, a cloud-based network with a remote server cluster can be conveniently constructed, and this network is suitable for a wide area spectrum cognition or big data collection for machine learning.

III A Full-Dimension MIMO system

In this section, a constructive example is provided to validate the feasibility and flexibility of our proposed system architecture by establishing a multi-user full-dimension MIMO prototyping system.

III-A Signal Model

Considering a multi-user full-dimension MIMO communication system, where $K$ single-antenna user equipments (UEs) communicate with a base station (BS) having an $L_{1}\times L_{2}$ uniform planar antenna array, we apply an orthogonal frequency division multiplexing (OFDM) technology. Different users transmit frequency orthogonal pilots in the uplink training phase. Additionally, least square (LS) channel estimation and linear minimum mean square error (LMMSE) detector are employed in the base station. The transmission procedure is divided into two phases, namely, the training phase and data transmission phase, which are consistent with those used in our past work [11].

III-B Prototype Setup

To implement the multi-user full-dimension MIMO communication system with the proposed system architecture, we employ eight SDR nodes of the USRP RIO series manufactured by National Instruments. Each SDR node consists of two RF transceivers of 120 MHz bandwidth and a programmable FPGA responsible for distributed signal processing, such as reciprocity calibration or OFDM (de)modulation. Fig. 2(d) shows the assembled multi-user full-dimension MIMO communication system comprising a clock distribution module, an FPGA-coprocessor card configured with four 10G Ethernet ports, a high-data throughput PXI chassis, a server containing 20 Intel Xeon E5-2680 v2 @2.8 GHz processors, and two small form-factor pluggable plus (SFP+) cables.

Similar to the frame structure described in our previous study [11], a simplified LTE-like 10 ms radio frame structure is used. In this structure, Subframe 0 is used for synchronization and Subframes 1-9 are used for uplink and downlink data transmission. Once a successful synchronization occurs between BS and UEs, frequency orthogonal uplink pilot OFDM symbols followed by uplink data OFDM symbols are transmitted from four single-antenna users. The RF signals acquired by the $8\times 2$ antenna array are initially delivered to eight SDR nodes for down conversion and OFDM demodulation. The obtained baseband data are subsequently converged in the FPGA-coprocessor through the PXI chassis for bandwidth splitting and UDP packaging. Then, UDP-packaged data are conveyed to the server by two 10G Ethernet ports and two SFP+ cables.

According to the labels contained in each UDP packet header, signal processing tasks in a server are arranged to nine threads in parallel, and each thread performs the task of one subframe data processing. The signal processing tasks include the channel estimation and MIMO detection. In Fig. 2(e), the following 13 parallel threads are found in the server for our 16-antenna system: one main thread (represented by yellow), two UDP receive threads (represented by green), nine subframe processing threads (represented by red), and one UDP transmission thread (represented by purple). Each thread is allocated with an individual CPU core. Thus, 13 of the 20 CPU cores in the server are leveraged and displayed by the system monitor in Fig. 2(a).

Two UDP receive threads collect data from the FPGA-coprocessor via two 10G Ethernet ports. Nine subframe processing threads are used for nine subframe data processing, and one UDP transmit thread is utilized for demodulated data transfer from the server to the video client for the constellation and video display. The main thread is utilized to schedule the other threads. Moreover, the procedures of the nine subframe processing threads are consistent, except the data to be processed are from different subframes with respect to that task arrangement. Specifically, the data of Subframes 1 and 2 are processed in the Subframe 1 and the Subframe 2 Processing Threads, respectively. The same process occurs in the other subframes. The detailed processing procedures of each subframe processing thread and the UDP receive thread are illustrated in Fig. 3.

III-C Experiment Results

To validate the feasibility and flexibility of the proposed system architecture, we provide our experimental results in terms of data transmission, CPU load analysis, and data streaming analysis based on proposed multi-user full-dimension system.

Data transmission. In the prototype system [Figs. 2(b)-(d)], the carrier frequency is 4.1 GHz, the sample rate is 30.72 MS/s, and the data transmission bandwidth is 20 MHz. QPSK is adopted by user 0, and the three other users use 16-QAM. Under the current settings, video transmission is successful. We also test 64-QAM and 256-QAM for data transmission. With the assistance of channel estimate interpolation, we find that 64-QAM can successfully perform video transmission while much mosaic appears in 256-QAM. This finding indicates that the channel coding is necessary.

CPU load analysis. In implementing the algorithm in multi-core GPP, the CPU load representing the duty cycle of CPU cores requires analysis. The calculated CPU cycles and theoretical duty cycle under different scenarios are listed in Table I. Approximately $4.806\times 10^{6}$ cycles or $\frac{{4.806\times{{10}^{6}}}}{{2.8\times{{10}^{9}}}}=1.716$ ms are spent by each core to process the signals of the 16-antenna system with four single-antenna users. The theoretical duty cycle is 17.16% based on the 10 ms radio frame structure. This theoretical value nearly matches the practical duty cycle of 18.7% [Fig. 2(a)] when some trivial operations are disregarded. Table I also indicates that the computation capability of the server is sufficient to handle 12 users regardless of whether a 16- or 128-antenna system is used. Clearly, a wideband or a large-scale antenna prototyping system with more advanced CPU cores can be applied.

Data streaming analysis. In configuring one uplink pilot symbol and two uplink data symbols per slot (except for Subframe 0) with 16-bit (or 2-byte) analog-to-digital converter (ADC), the theoretical data rate of two 10G Ethernet ports is $30.72({\rm{MS/s}})\times\frac{{1200\times 54}}{{307200}}\times 2({\rm{I,Q}})\times 2({\rm{bytes}})\times 16({\rm{antennas}})=414.72{\rm{MB/s}}$, nearly matching the practical data rate $413.3{\rm{MB/s}}$ displayed in Fig. 2(a). Hence, each port is approximately $414.72{\rm{MByte/s}}\times 8/2\approx 1.7$ Gbps $<$ 10 Gbps, which is the line rate of 10G Ethernet port and indicates the potential of a 128-antenna system utilizing four 10G Ethernet ports individually running at 6.6 Gbps. Increased data throughput, widened bandwidth, and additional antennas can also be supported by maximizing FPGA-coprocessor cards and transplanting channel estimation into FPGA.

Superiority analysis. Table III-C compares existing prototyping systems. Owing to the short compiling time (e.g., several seconds in GPP) and the unnecessary conversion from floating-point calculation to fixed-point calculation, the comparison of Argos and LuMaMi shows that RaPro can satisfy the real-time requirements of large antenna arrays and a wide transmission bandwidth with a significantly shorter development period. Meanwhile, RaPro breaks the performance bottleneck in the BigStation and OAI testbeds using a customized software architecture in GPPs while maintaining priorities and flexibilities in developing innovative algorithm.