A Software-equivalent SNN Hardware using RRAM-array for Asynchronous Real-time Learning

TL;DR

This paper presents a RRAM-array based hardware design for asynchronous real-time learning in spiking neural networks, addressing key challenges in recognition accuracy, hardware-software emulation, and device realism.

Contribution

It introduces a novel asynchronous hardware architecture that separates learning and recognition arrays, closely emulates software, and uses realistic memristor models for improved SNN implementation.

Findings

97.5% classification accuracy on Fisher-Iris dataset

Hardware performance slightly decreases to 85% with realistic memristor models

Separate arrays enable real-time asynchronous learning and recognition

Abstract

Spiking Neural Network (SNN) naturally inspires hardware implementation as it is based on biology. For learning, spike time dependent plasticity (STDP) may be implemented using an energy efficient waveform superposition on memristor based synapse. However, system level implementation has three challenges. First, a classic dilemma is that recognition requires current reading for short voltage$-$spikes which is disturbed by large voltage$-$waveforms that are simultaneously applied on the same memristor for real$-$time learning i.e. the simultaneous read$-$write dilemma. Second, the hardware needs to exactly replicate software implementation for easy adaptation of algorithm to hardware. Third, the devices used in hardware simulations must be realistic. In this paper, we present an approach to address the above concerns. First, the learning and recognition occurs in separate arrays simultaneously in real$-$time, asynchronously $-$ avoiding non$-$biomimetic clocking based complex signal management. Second, we show that the hardware emulates software at every stage by comparison of SPICE (circuit$-$simulator) with MATLAB (mathematical SNN algorithm implementation in software) implementations. As an example, the hardware shows 97.5 per cent accuracy in classification which is equivalent to software for a Fisher$-$Iris dataset. Third, the STDP is implemented using a model of synaptic device implemented using HfO2 memristor. We show that an increasingly realistic memristor model slightly reduces the hardware performance (85 per cent), which highlights the need to engineer RRAM characteristics specifically for SNN.