# Loop Tiling in Large-Scale Stencil Codes at Run-time with OPS

**Authors:** Istvan Z Reguly, Gihan R Mudalige, Mike B Giles

arXiv: 1704.00693 · 2017-11-30

## TL;DR

This paper introduces a run-time optimization technique called iteration space slicing for large-scale stencil codes, achieving significant speedups and scalability improvements on supercomputers by enhancing data locality in complex PDE applications.

## Contribution

It adapts iteration space slicing for large OPS applications, enabling effective data locality optimization through run-time analysis in distributed and shared-memory systems.

## Key findings

- 2x speedup on Cloverleaf proxy application
- 3.5x speedup on TeaLeaf linear solver
- Maintained throughput on large problem sizes with scalability up to 8704 cores

## Abstract

The key common bottleneck in most stencil codes is data movement, and prior research has shown that improving data locality through optimisations that schedule across loops do particularly well. However, in many large PDE applications it is not possible to apply such optimisations through compilers because there are many options, execution paths and data per grid point, many dependent on run-time parameters, and the code is distributed across different compilation units. In this paper, we adapt the data locality improving optimisation called iteration space slicing for use in large OPS applications both in shared-memory and distributed-memory systems, relying on run-time analysis and delayed execution. We evaluate our approach on a number of applications, observing speedups of 2$\times$ on the Cloverleaf 2D/3D proxy application, which contain 83/141 loops respectively, $3.5\times$ on the linear solver TeaLeaf, and $1.7\times$ on the compressible Navier-Stokes solver OpenSBLI. We demonstrate strong and weak scalability up to 4608 cores of CINECA's Marconi supercomputer. We also evaluate our algorithms on Intel's Knights Landing, demonstrating maintained throughput as the problem size grows beyond 16GB, and we do scaling studies up to 8704 cores. The approach is generally applicable to any stencil DSL that provides per loop data access information.

## Full text

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## Figures

7 figures with captions in the complete paper: https://tomesphere.com/paper/1704.00693/full.md

## References

47 references — full list in the complete paper: https://tomesphere.com/paper/1704.00693/full.md

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Source: https://tomesphere.com/paper/1704.00693