Fast Encoding and Decoding of Flexible-Rate and Flexible-Length Polar Codes
Muhammad Hanif, Masoud Ardakani
TL;DR
This paper introduces parallel decoding and fast encoding techniques for polar codes, significantly reducing latency and increasing throughput while supporting flexible rates and lengths.
Contribution
It proposes universal 8-bit and 16-bit parallel decoders and fast encoders for polar codes, enhancing decoding speed and encoder throughput.
Findings
Reduced decoding latency with parallel decoders
Increased encoder throughput with fast encoders
Supports flexible-rate and flexible-length polar codes
Abstract
This work is on fast encoding and decoding of polar codes. We propose and detail 8-bit and 16-bit parallel decoders that can be used to reduce the decoding latency of the successive-cancellation decoder. These decoders are universal and can decode flexible-rate and flexible-length polar codes. We also present fast encoders that can be used to increase the throughput of serially-implemented polar encoders.
| (Binary) | (Hex) | Output, | |||
|---|---|---|---|---|---|
| 0 | FF | {} | - | ||
| 1 | FE | {7} | 8 | ||
| FC | {6,7} | 4 | |||
| 2 | FA | {5,7} | 4 | ||
| EE | {3,7} | 4 | |||
| F8 | {5,6,7} | 4 | |||
| 3 | EC | {3,6,7} | 4 | ||
| EA | {3,5,7} | 4 | |||
| 4 | E8 | {3,5,6,7} | 4 | ||
| F0 | {4,5,6,7} | 2 | |||
| CC | {2,3,6,7} | 2 | |||
| AA | {1,3,5,7} | 2 | |||
| E0 | {3,4,5,6,7} | 2 | |||
| 5 | C8 | {2,3,5,6,7} | 2 | ||
| A8 | {1,3,5,6,7} | 2 | |||
| C0 | {2,3,4,5,6,7} | 2 | |||
| 6 | A0 | {1,3,4,5,6,7} | 2 | ||
| 88 | {1,2,3,5,6,7} | 2 | |||
| 7 | 80 | {1,2,3,4,5,6,7} | 2 | ||
| 8 | 00 | {0,1,2,3,4,5,6,7} | 1 |
| (Hex) | Output, | ||
|---|---|---|---|
| 0 | FFFF | - | |
| 1 | FFFE | 16 | |
| 2 | FFFC | 8 | |
| 3 | FFF8 | 8 | |
| 4 | FFE8 | 8 | |
| 5 | FEE8 | 8 | |
| 6 | FFC0 | 4 | |
| FEE0 | 4 | ||
| 7 | FF80 | 4 | |
| FEC0 | 4 | ||
| 8 | FE80 | 4 | |
| FCC0 | 4 | ||
| 9 | FC80 | 4 | |
| 10 | F880 | 4 | |
| 11 | E880 | 4 | |
| 12 | E800 | 2 | |
| C0C0 | 2 | ||
| 13 | E000 | 2 | |
| 14 | C000 | 2 | |
| 15 | 8000 | 2 | |
| 16 | 0000 | 1 |
| Latency, | Latency, | Latency, | |||
|---|---|---|---|---|---|
| Case 0 | 0 | Case 0 | 0 | Case 8 | |
| Case 1 | 1 | Case 1 | 1 | Case 9 | |
| Case 2 | 1 | Case 2 | 1 | Case 10 | |
| Case 3 | 1+ | Case 3 | 1+ | Case 11 | |
| Case 4 | Case 4 | Case 12 | |||
| Case 5 | Case 5 | Case 12 | |||
| Case 6 | Case 6 | Case 13 | |||
| Case 7 | Case 6 | Case 14 | |||
| Case 8 | 0 | Case 7 | Case 15 | ||
| Case 7 | Case 16 | 0 | |||
| Case 8 | |||||
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsError Correcting Code Techniques · Advanced Wireless Communication Techniques · DNA and Biological Computing
Fast Encoding and Decoding of Flexible-Rate and Flexible-Length Polar Codes
Muhammad Hanif and Masoud Ardakani M. Hanif and M. Ardakani are with the Department of Electrical and Computer Engineering, University of Alberta, AB, Canada (email: [email protected], [email protected]).
Abstract
This work is on fast encoding and decoding of polar codes. We propose and detail 8-bit and 16-bit parallel decoders that can be used to reduce the decoding latency of the successive-cancellation decoder. These decoders are universal and can decode flexible-rate and flexible-length polar codes. We also present fast encoders that can be used to increase the throughput of serially-implemented polar encoders.
Index Terms:
Polar codes, domination contiguity, maximum a posteriori, maximum likelihood, minimum distance, systematic codes, non-systematic codes.
I Introduction
Polar codes are capacity-achieving block codes that are recently introduced by Arıkan [1]. Due to their provable capacity-achieving performance with low-complexity encoding and decoding, they have gained significant interest [2, 3]. In particular, polar codes can be encoded and decoded in a recursive fashion, which results in encoding and decoding complexities of , where is the code length [1].
One of the main challenges associated with polar codes is their high decoding latency and low throughput [4, 2]. Since the serial nature of decoding bottlenecks fast implementation of polar coding, researchers have introduced novel ways to reduce the decoding time [3, 5, 2, 6, 4]. For example, [5] introduces the notion of rate-zero and rate-one nodes to reduce the decoding depth of the successive cancellation (SC) decoder. The resulting simplified SC (SSC) decoder reduces the decoding latency up to 20 times [6]. The decoding latency can further be improved by identifying single-parity-check (SPC), repetition (REP) and REP-SPC nodes in the decoding tree of polar codes and implementing their fast decoders [2].
The key idea behind the above-mentioned strategies is to increase the decoding speed by reducing the decoding depth and implementing fast parallel decoders for some particular frozen-bit sequences. As such, these schemes work only on specific codes. In particular, the decoding tree of a given rate and length polar code is first constructed, and then the afore-mentioned nodes are identified and implemented in hardware. Changing the code length or rate will necessitate re-identification of these nodes. As such, these schemes are not suitable for variable-rate and/or variable-length polar codes.
The new radio access technology will use a variable rate and length polar code for downlink control information to fully utilize the physical resources [7, 8, 9]. As such, implementing fast polar decoders that work for any rate and length is of practical interest. One such decoder, that reduces the decoding depth by one was proposed in [10]. In particular, the authors proposed to decode two bits in parallel by implementing four decoders corresponding to all frozen-bit sequences. The same authors then extended this concept to larger power of 2 block sizes in [11, 12], but the extension results in huge hardware cost as the number of all frozen-bit sequences grows exponentially with the block size. Secondly, their decoding methodology does not identify and utilize the code structure for different frozen-bit sequences to reduce the hardware area or computational complexity.
In this paper, we present fast decoders for variable-rate and/or variable-length polar codes. In particular, we borrow the idea presented in [10, 11, 12] of implementing -bit () parallel decoders at the last stage. But, unlike [10, 11, 12], we do not implement parallel decoders for decoding each contiguous block of bits. Rather, we rely on a key characteristic of properly-designed polar codes, domination contiguity of the set of good bit-channel indexes [3], to significantly reduce the required number of parallel decoders for each block. Additionally, we use the minimum distance of the polar code corresponding to each domination-contiguous set to further reduce the number of required decoders. For example, we implement only instead of parallel decoders for , which implies that the required number of decoders is reduced by 99.97% compared to a simple application of ideas presented in [11, 12].
Achieving hardware-area reduction is not the only aim of our proposed decoding strategy. We also reduce the decoding complexity by relying on specific structure of the polar code corresponding to each bit-channel index set. We aim to minimize computationally-intensive operations, such as check-node operations, while ensuring that the proposed parallel decoders do not tangibly alter the performance of the SC decoder.
Unlike decoding, which is serial in nature, encoding of polar codes can be done in parallel. In fact, the seminal work on polar codes presented a fully-parallel encoding architecture for non-systematic polar codes [1]. Although very high encoding speed can be achieved by implementing a fully-parallel encoder, such an implementation is highly disadvantaged due to large memory size and number of XOR gates, especially for long polar codes. As such, folded or serial implementations of polar-code encoders are implemented to reduce the hardware area [13]. Moreover, systematic polar codes, as proposed in [14], are serial by nature.
Like decoding, the serial implementation of polar encoder results in higher encoding latency. Similar to our proposed decoding strategy, we can increase the encoding speed by implementing -bit parallel encoders at the last stage. Such an implementation is particularly helpful for flexible-rate and/or flexible-length systematic polar codes as they are non-trivial to be parallelized due to their bidirectional information transfer [14, 2, 3].
Our main contributions are summarized in the following.
We present fast parallel decoders for variable-rate and variable-length polar codes. In particular, we detail 9 (instead of ) decoders for 8-bit parallel decoding and 21 (instead of ) decoders for 16-bit parallel decoding of polar codes. These decoders accommodate all frozen-bit sequences that can occur in a block of 8 or 16 bits. 2. 2.
Secondly, our scheme improves the encoding speed of serially-implemented variable-rate or variable-length polar codes. Our scheme is particularly useful for flexible-rate or flexible-length systematic polar codes as their encoding is hard to be parallelized.
In the following, we first provide a background on polar codes in Section II, primarily to establish some notations and explain the challenges associate with variable-rate polar codes. We also review the domination contiguity of the set of good bit-channel indexes in Section II. We then present our proposed -bit parallel encoder/decoders in Section III. Afterwards, we present some numerical results for corroboration of our proposed scheme, which will be followed by concluding remarks in Section V.
Although we will be focussing mainly on the systematic polar codes (due to their superior performance and difficulty in parallelization [14, 3]), similar results and conclusions can be drawn for non-systematic polar codes with little or no modifications.
II Background
II-A Encoding Polar Codes
Polar codes defined on the binary field, , are block codes, which can be mathematically described as
[TABLE]
where is the codeword of length , is the input vector comprising information and frozen bits, and denotes the generator matrix. The matrix for non-reversed polar codes111For the sake of exposition, we consider only non-reversed polar codes as similar conclusions can be drawn for reversed-polar codes with proper permutation. is , where is the th tensor power of defined as
[TABLE]
with . Denoting the left and right halves of () by and ( and ), respectively, (2) implies , and . Consequently, a message vector of length can be encoded by encoding two message vectors of length each. Repeating this process times results in encoding message bits individually. As such, polar codes have a low encoding complexity of .
II-B Constructing Polar Codes
Polar codes rely on the phenomenon of channel polarization, which constructs polarized bit channels out of independent copies of a given binary memoryless channel, . In particular, copies of are combined and then split to a set of binary-input channels, , where , such that the symmetric capacity of tends towards either [math] or as becomes large. Bit channels having near-unity symmetric capacity are identified as ‘good’ channels, whereas the others are classified as ‘bad’ channels and are frozen to zero [1]. Mathematically, denoting the set of ‘good’ and ‘bad’ bit-channel indexes by and , respectively, .
II-C Decoding Polar Codes
Since a polar code can be encoded recursively, it can be represented by a binary tree, where each node represents a codeword [5, 2]. Fig. 1 (a) shows such a tree corresponding to a polar code of length 16, where the white and black leaves correspond to frozen and information bits, respectively.
We explain different decoding algorithms using the tree representation as follows. In the SC decoder [1], the root node receives , the channel log-likelihood ratios (LLR). Denoting the left and right halves of by and , respectively, the root node sends the outputs of check-node operations between and to its left child. Mathematically, the left child receives , a vector of real numbers whose th element, , is computed as
[TABLE]
where and are the th element of and , respectively.
Afterwards, the left child performs decoding on (which we will explain later) and returns a binary vector, , to the root node. The root node then computes and sends it to the right child. The th element of , , is computed as
[TABLE]
where is the th element of . The right child then performs decoding similar to the left child and returns a binary vector, , to the root node. The root node then returns an estimate of the codeword based on and as
[TABLE]
where the vector addition is performed in .
For non-systematic polar codes, the left and right children also return and , respectively, to the root node. These binary vectors are estimates of the left and right halves of the input, . The root node, in addition to computing , computes an estimate of as .
Since each child of the root node can be considered as the root node of a subtree, each child performs exactly the same operation of its parent node. This process continues until the leaf nodes receive real-valued messages from their parents. Since leaf nodes do not have any child, they either send 0 or hard-decision estimates based on the received LLRs to their parents depending on the frozen-bit sequence.
The decoding latency of the SC decoder depends on the computation time of the check-node operation and the decoding-tree depth. The SSC decoder [5] improves the latency by identifying and removing descendants of rate-0 and rate-1 nodes in the code tree as shown in Fig. 1 (b). Here, instead of traversing (which involves performing check-node operations) the subtree rooted in a rate-0 node, an all-zero vector is sent to its parent node. Similarly, a rate-1 node computes and sends the binary vector(s) to its parent node without traversing its descendants.
The fast-SSC decoder [2] further prunes the decoding tree by identifying the SPC, REP and REP-SPC nodes in the tree. For example, in Fig. 1 (c), the subtrees of two SPC nodes are removed from the tree resulting in the decoding depth of only two.
As clear from Fig. 1, both the SSC and fast-SSC decoders require identification of some special nodes based on the frozen-bit sequence, which can be used to eliminate corresponding subtrees in the code tree. In polar codes with flexible rate or length, the frozen-bit sequence changes with the code rate and length (see Fig. 2). Hence, these algorithms are not directly applicable.
For variable-rate or variable-length polar codes, -bit parallel decoders as proposed in [10, 11, 12] can be used to improve the decoding speed, where . Fig. 2 shows such a case where a -bit parallel decoder is implemented to decode a variable-rate polar of length . Here, the frozen-bit sequence is represented in hexadecimal notation. For example, when the frozen-bit sequence is FFFE, all bits except the last one are frozen to zero in a block of 16 bits.
Observe that, unlike Fig. 1 (b) and (c), the code-tree structure remains the same regardless of the code rate. Secondly, the code tree is also complete, i.e., all nodes except the leaf nodes have two children. A similar observation can be made about Fig. 1 (d) and (e), where 8-bit and 16-bit parallel decoders are used to improve the decoding speed, respectively.
The -bit parallel decoders must be able to decode all the frozen-bit sequences that can occur in a block of bits. One way to satisfy this requirement is to implement parallel sub-decoders and select the appropriate one corresponding to the frozen bit sequence as proposed in [10, 11, 12]. Unfortunately, this solution becomes impractical even for small values of . However, we can reduce the required number of decoders by using a key characteristic of properly-designed polar codes, domination contiguity, as described below.
II-D Domination Contiguity
Let denote the set , where , and is a positive integer. For , we use to represent the -bit binary representation of , i.e., , where is the most-significant bit. For , is said to binary dominate , denoted by , if and only if for all , where and are the th least-significant bits in the binary representations of and , respectively. A set, , is domination contiguous if and implies .
For a properly-designed polar code, the set of good bit-channel indexes, , must be domination contiguous [3]. Since not all subsets of are domination contiguous, the cardinality of the set of all possible frozen-bit sequences of a properly-designed polar code is less than . In the following, we will explain how this key characteristic can be used to significantly reduce the number of required decoders from for -bit parallel decoders.
III Proposed Encoder/Decoder Structure
The proposed encoders/decoders rely on parallel encoding/decoding of bit channels simultaneously, where , and is a positive integer. Specifically, we divide -bit into consecutive groups each containing bits, i.e., . Then we encode/decode bits in each group simultaneously to reduce the encoding/decoding depth of the code tree by levels.
Quite intuitively, the greater the value of , the faster the encoder/decoder will be. On the downside, we require more hardware to implement all the encoders/decoders for a block size of . Theorem 1 describes inheritance of domination contiguity of to the domination contiguity in each block of bits, which will be used later to optimize the number of required encoders/decoders for an -bit parallel decoder.
Theorem 1**.**
Let denote the set of good bit-channel indexes corresponding to , . For a properly-designed polar code, is domination contiguous.
Proof:
Observe that all elements of each have the same most-significant bits, where , and . Further, the most-significant bits corresponding to each differ in at least one bit from that of , where , and . Domination contiguity of implies that if and then . But and have the same most-significant bits. As such, implies that also has the same most-significant bits. Therefore, . ∎
An immediate consequence of the domination contiguity of ’s is that the number of required encoders/decoders can be reduced from . The following theorem shows that the number of all domination-contiguous sets becomes significantly less than as grows to infinity.
Theorem 2**.**
Let denote a universal set containing all the good bit-channel indexes of the th -bit block, , for . Denoting the cardinality of a set by , the ratio is a decreasing function of , and in the limit as goes to infinity, the ratio goes to zero.
Proof:
Without loss of generality, we consider the first -bit block (). Furthermore, we let and split the elements of any into two sets, and , where contains those elements of that are less than , and contains the remaining.
Theorem 1 asserts that the domination contiguity of begets domination contiguity of and . Consequently, , where , , , and . Clearly, , and as such, .
Moreover, if then [2]. Equivalently, implies . Conversely, if then and . But contains those sets which correspond to and . Therefore, , and .
Lastly, we define a sequence , where , and . Using the fact that and , we get . ∎
Theorem 2 shows that the ratio is a decreasing function of . But it does not imply that does not increase rapidly. In fact, can be shown to be equal to , , , , , and for and , respectively. Clearly, implementing parallel decoders to increase the decoding speed becomes impractical even for moderate block lengths. Fortunately, we can reduce the number of required decoders further by eliminating some frozen-bit sequences depending on the minimum distance of the corresponding code and the position of frozen bits in the sequence as explained below. Note that the minimum required number of encoders/decoders corresponding to each block of bits is because the number of frozen bits in a block of bits can vary from [math] to . Hence, at least encoders/decoders are needed. A solution based on encoders/decoders, if exists, has minimized the hardware area.
In the following, we present encoders for all the cases corresponding to for . Later, we reduce this number to the minimum, i.e. 9, based on the position of frozen bits and the minimum distance of the polar code corresponding to each frozen-bit sequence. To do so, we define the notion of max-frozen set, which will be used to eliminate some candidate sets.
Let denote a bit-permutation function that maps to such that the bits in are a permutation of the bits in . Further, for , we define . For example, the bit-reversal permutation [1] for maps to , where , and . Likewise, if then .
Lemma 1**.**
If is domination contiguous then so is .
Proof:
Let be the inverse permutation function, i.e., . Further, let and . As such, . Also, we observe that binary domination is invariant to bit permutations, i.e., implies . Since domination contiguity of implies , . Therefore, is domination contiguous. ∎
Let denote the permutation matrix corresponding to the bit-permutation function . Here, denotes a column vector whose th element is 1 and the remaining elements are 0. It was shown in [15, 16] that . Therefore, . Denoting and , we get . Consequently, if is a polar code for input then permuting the bit positions of permutes in the same manner. We refer these codes to be the conjugates of the original code. Observe that the set of good bit-channel indexes of a conjugate polar code is .
Lemma 1 confirms that, similar to , is domination contiguous. Further, when differs , the SC decoding shows worse performance [16]. However, the SC decoder can be modified to decode in the permuted order [15, 16] to achieve the same performance. Consequently, for a given decoding order, only one set of good bit-channel indexes will show the best performance. Quite intuitively, the set which results in early ‘decoding’ of the most frozen bits will outperform others [17, Section 7.4.3]. We call this set the max-frozen set. As such, for a given decoding order, the number of required decoders can be reduced by implementing decoders only for the max-frozen sets and ignoring their distinct bit-permuted sets.
In the following, we present encoders and decoders for . For the sake of clarity, we will drop the subscript from . Also, the set of frozen bit-channel indexes will be represented by . Lastly, we will consider the natural-order decoding of polar codes to eliminate all the bit-permuted sets of the max-frozen set.
III-A Block Size 8 Encoders/Decoders
Table I enlists all the 20 frozen-bit sequences, , that can occur in a block of 8 consecutive bit channels of a properly-designed polar code. The th component of is 1 if the th bit channel is frozen and is 0 otherwise. These sequences are grouped into 9 different cases depending on the number of information bits in the block of 8 bits. The corresponding set of good bit-channel indexes are also tabulated. Observe that all the sets are domination contiguous. Lastly, the systematic polar code, , corresponding to each frozen-bit sequence is also mentioned along with its minimum distance, . As we explain below, the code structure and its corresponding frozen-bit sequence and will be used to further reduce the number of possible cases from 20 to 9. For the sake of brevity, we have used the notation to denote .
In the following, we discuss each individual case and explain why a particular frozen-bit sequence is kept in each case.
III-A1 Case 0
This case corresponds the rate-0 node introduced in [5], and the optimal decoder assigns an all-zero vector to the output.
III-A2 Case 1
This is an repetition code, and the optimal maximum-likelihood (ML) decoder will add the LLRs of all the channel outputs and perform threshold detection on the sum [18]. The same decoder is used in [2], where they have outlined some low-latency decoding strategies for improving the decoding speed.
III-A3 Case 2
All the three cases are repetition codes and are conjugates of one another. For the SC decoder with natural-order decoding, the first case is the max-frozen set. Consequently, other cases will not occur. The optimal decoder, like Case 1, will add the LLRs of four outputs to estimate and other four LLRs to estimate .
III-A4 Case 3
These codes are concatenated (8,4) repetition and (4,3) single parity-check (SPC) codes and are conjugates of one another. Since is the max-frozen set, only the first case will occur in practice. The decoding can be carried out by first adding the LLRs of the outputs corresponding to the same bits. As such, we are left with the LLRs of a (4,3) SPC code. The optimal ML decoder of the SPC codes, Wagner decoder [19], makes hard-decision estimates of ’s and flips the least-reliable bit if the parity check is not satisfied.
III-A5 Case 4
The number of good bit-channel indexes, , is 4 when . Amongst them, three correspond to repetition codes. As such, their . In only one case, , the minimum distance turns out to be 4. Since code performance heavily depends on , only this case will occur in practice. In fact, this is an extended Hamming code [20] and is equivalent to the repetition-SPC code introduced in [2]. Although the optimal ML decoder for such a code can be implemented easily [18], a low-complexity decoder of this code was mentioned in [2]. Furthermore, the bit-error rate (BER) performance of the code is not considerably altered by implementing the low-complexity decoder instead of the optimal decoder [2]. For completeness, we briefly mention the low-complexity decoder below.
First, observe that constitute a (4,1) repetition code, while is a (4,3) SPC code. The repetition code can easily be decoded by adding the LLRs, resulting in , a hard-decision estimate of . Afterwards, additional LLRs for are trivially computed either by keeping or switching the sign of the LLRs of depending on the value of . After adding the LLRs of , we are left with a (4,3) SPC code, which can be decoded by the Wagner decoder.
III-A6 Case 5
Observe that all the codes are conjugate of one another, and is the max-frozen set. Thus, only the first case will occur in practice. By introducing an additional node, , a cycle-free Tanner graph of the code can be obtained as shown in Fig. 3. As such, a non-iterative optimal maximum-a-posteriori (MAP) decoder can be implemented [21].
Like Case 4, a low-complexity sub-optimal decoder can also be implemented by first making a hard decision about . Afterwards, depending on , LLRs of can be added or subtracted to that of . Hard decisions of can then be carried out, which along with can be used to find estimates of . The decoding latency can be reduced by implementing two parallel decoders assuming equals 0 or 1 and selecting the appropriate output depending on the actual value of . Also, as verified by the simulation results, the BER performance is not tangibly degraded by implementing the sub-optimal decoder instead of the optimal MAP decoder.
III-A7 Case 6
All of the codes conjugates of one another. But the first case will occur in practice as is the max-frozen set. Since this code is just two (4,3) SPC codes put together, two Wagner decoders can be used to optimally decode it.
III-A8 Case 7
This is an (8,7) SPC code, and the Wagner decoder can be used to optimally decode it. Note that this code is equivalent to the one corresponding to the SPC node mentioned in [2], which were introduced to increase the decoding speed, especially for high-rate polar codes.
III-A9 Case 8
This case is equivalent to the rate-1 node introduced in [5], and a hard decision of the observed outputs gives the decoded output.
Remark 1**.**
For non-systematic codes, exactly the same decoders can be used to find a hard-decision estimate of , which can be used to decode the input, . For example, for , , which is an (8,2) repetition code. Like in Case 2, we can find hard-decision estimates of and , which can be used to find a hard-decision estimate of .
Remark 2**.**
For permuted polar codes, similar conclusions can be drawn as the set of good bit-channel indexes is also domination contiguous for permuted (systematic/non-systematic) polar codes. In particular, the max-frozen sets for an individual case will be determined according to the permuted decoding order. Also, the presented low-complexity decoders can trivially be modified to decode the polar codes corresponding to the max-frozen sets.
Remark 3**.**
Implementing the proposed low-complexity decoders reduces the number of check-node operations significantly. In particular, the SC decoder uses 12 check-node operations for decoding 8 bits for each of the afore-mentioned cases. In our case, however, baring Case 4 and Case 5, check-node operations are not used. Furthermore, decoders of Case 4 and Case 5 use only 4 check-node operations, which are implemented in parallel. As such, compared with the SC decoder, where 12 check-node operations are used and are carried out sequentially, the proposed decoders require less check-node operations and are faster as these operations can be implemented in parallel.
III-B Block Size 16 Encoders/Decoders
Having discussed all the possible cases for , we now consider polar codes for . Similar to case, we can significantly reduce the required number of parallel encoders/decoders (from 168 to just 21). Table II enlists these 21 cases along with the of the corresponding codes. Here, we have used hexadecimal indexes for the sake of brevity. The appendix provides a detailed description of the proposed decoders for the cases tabulated in Table II.
It is worth noting that at least 17 encoders/decoders are required for encoding/decoding flexible-rate polar codes. So only four extra encoders/decoders are needed to ensure that the polar codes designed for any rate, length and channel can be encoded/decoded. The following theorems assert that the encoders/decoders for , , , and are not required when polar codes are designed for a binary-erasure channel (BEC) or by Huawei formula [7].
Theorem 3**.**
If polar codes are constructed for a BEC, encoders/decoders for , , , and are not required.
Proof:
This assertion can be proved by noting that, regardless of the value of erasure probability, the afore-mentioned four cases do not occur when . The result immediately follows by noting that the frozen-bit sequence for each of 16-bit block is generated for a BEC [1]. ∎
Recently, in 3GPP RAN1 #87 meeting, an agreement was reached to use variable-rate polar codes for uplink control channel [9, 7]. Since polar-code design is channel dependent, and the location of frozen bits varies with the channel conditions, Huawei presented a channel-independent reliability metric for constructing polar codes [7]. In particular, each polarized bit-channel, , is assigned a reliability metric, , computed as
[TABLE]
where is the th least-significant bit in the -bit binary representation of , i.e., .
The following theorem asserts that the extra cases are not required when polar codes are constructed by Huawei formula.
Theorem 4**.**
If polar codes are constructed by using Huawei formula, the four extra case (, , , and ) do not occur at all.
Proof:
Observe that
[TABLE]
Next, we partition into consecutive groups, each containing 16 numbers. By denoting them with , where , we have and . Further, observe that of all the elements in have exactly the same value of . As such, inclusion of in depends solely on , or the last four bits of . Letting denote the decimal number corresponding to the last 4 bits of , we observe that the values of decreases monotonically when takes on values from left to right. As such, for Case (), the first bit-channel indexes are selected in for information transfer, and the rest are frozen to zero. Consequently, only 17 unique cases will occur, and the afore-mentioned four extra cases will not occur. ∎
IV Results
In this section, we compare the proposed decoding strategy with the SC decoder in terms of the bit-error-rate and decoding latency performances.
IV-A BER Performance
Fig. 4 compares the BER performance of the proposed 8-bit parallel decoders with that of the SC decoder. Both optimal and low-complexity sub-optimal decoders are implemented for the proposed decoders. Here, the polar codes are constructed for the binary-erasure channel with the erasure probability of [22, 23].
Some interesting observations can be made by analyzing the figure. First, the proposed decoders do not deteriorate the performance of the SC decoder. Second, the performance gap between the optimal and the sub-optimal decoders is negligibly small, which implies that the low-complexity decoders can be used instead of the optimal ones. Last, the proposed schemes can be used for both systematic and non-systematic polar codes.
IV-B Decoding Latency
One way to approximate the decoding latency of different polar decoders is as follows. We presume that bit operations and addition/subtraction of real numbers can be carried out in one clock cycle, whereas a check-node operation takes and finding the minimum of a list takes clock cycles. Note that finding a minimum requires significantly less computations than performing a check-node operation [24].
For a block of bits, the SC decoder performs check-node operations in each of stages. But all the check-node operations can be performed in parallel in the first stage, whereas the last stage requires all check-node operations to be performed in a sequential manner. In general, the number of parallel check-node operations performed in the th stage is , where . Consequently, a decoding latency of cycles is incurred in performing check-node operations for the SC decoder. Similarly, the number of binary and real additions involved in decoding bits be shown to be 1 and , respectively. Therefore, an SC decoder will take clock cycles to decode a block of bits. Note that this decoding latency is fixed regardless of the frozen-bit sequence.
For the proposed schemes, the decoding latency varies depending on the frozen-bit sequence. For example, for , Case 0 can be executed instantaneously, whereas Case 4 incurs the highest decoding latency of cycles, which is calculated as follows. The check-node operations are performed is parallel, so they take only cycles for execution. Meanwhile, two outputs can be generated corresponding to and by two Wagner decoders ( clock cycles), and, depending on the value of (computation time is 1 cycle), one of the outputs is selected. Therefore, the decoding latency for Case 4 is .
Observe that even the highest decoding latency of the proposed decoders is much smaller than that of the SC decoder. Hence, our proposed scheme will significantly improve the decoding speed of variable-rate polar codes.
Table III shows the decoding latency, , of the proposed low-complexity decoders for blocks of length and bits. Observe that the proposed decoders have significantly less decoding latency compared to the SC decoder, which has the decoding latency of cycles for all the cases.
V Conclusion
In this work, we presented fast 8-bit and 16-bit parallel decoders that can reduce the decoding-tree depth of the decoding tree of variable-rate and variable-length polar codes. They can reduce both the decoding latency and hardware complexity without deteriorating the bit-error-rate performance of the successive-cancellation decoder.
[Block Size 16 Decoders]
This appendix details the proposed low-complexity parallel decoders for the cases tabulated in Table II.
-1 Case 0
The optimal decoder assigns an all-zero vector to the output.
-2 Case 1
This is a repetition code, and the optimal decoder makes a hard decision on the sum of the LLRs of the received bits.
-3 Case 2
This is a (16,2) repetition code, and the optimal ML estimates of and can be found by making hard-decisions on the LLR sums of even-indexed and odd-indexed bits, respectively.
-4 Case 3
This is a (4,3) SPC code concatenated with a (16,4) repetition code. The optimal decoder will first add the LLRs of the received bits corresponding to , , , and before finding their hard estimates with the Wagner decoder.
-5 Case 4
This is an (8,4) extended Hamming code concatenated with a (16,8) repetition code. Decoders mentioned in Case 4 for can be used after adding the LLRs of the first half to the second’s.
-6 Case 5
Although an exhaustive-search based ML decoder can be implemented, we can reduce the decoding complexity by introducing a new variable, . By noting that , we first find , a hard-decision estimate of . Specifically, we add to get an LLR for and make a hard decision on the LLR to compute .
Afterwards, the decoder computes , where addition is performed when , and subtraction otherwise. These values are then input to one of the decoders of Case 4 for to get estimates of . Lastly is added to to compute .
Implementing two parallel decoders corresponding to equalling 0 and 1 and choosing an appropriate output after computing can reduce the decoding latency.
-7 Case 6
For the first case, , an optimal decoder can be implemented by noting that the codeword comprises two concatenated (4,3) SPC and (8,4) repetition codes. Two separate Wagner decoders can be used to find hard estimates of the transmitted bits after adding the LLRs of the repeated bits.
For the second case, , the decoder presented in Case 5 () can be used to decode the received LLRs with the exception that the decoder of Case 4 () is replaced with the low-complexity decoder of Case 5 ().
-8 Case 7
The first case, , corresponds to a concatenated (8,7) SPC and (16,8) repetition code. Therefore, the code can be decoded optimally by adding the LLRs of to that of and finding hard estimates by the Wagner decoder.
For the second case, , the decoder presented in Case 5 () can be used to decode the received LLRs with the exception that the low-complexity decoder of Case 6 () replaces the decoder of Case 4 ().
-9 Case 8
For the first case, , the decoder presented in Case 5 () can be used to decode the received LLRs with the exception that the Wagner decoder is used instead of the decoder of Case 4 ().
For the second case, , the even-indexed and the odd-indexed bits constitute two separate (8,4) extended Hamming codes. Therefore, the decoders for Case 4 () can be used to decode the received code vector.
-10 Case 9
A low-complexity decoder can be implemented by defining and . Observe that , and . The proposed decoder makes hard decisions on and and respectively assigns them to and , hard estimates of and , respectively. Afterwards, additional LLRs for are computed by using and . For example, the additional LLR of is when is 0 and otherwise. After adding the additional LLRs to , Wagner decoder is used to find hard estimates of , which along with and are used to estimate .
The decoding latency can be reduced by implementing four Wagner decoders (corresponding to four possible values of ) and using the computed value of to select the output of corresponding Wagner decoder.
-11 Case 10
A low-complexity decoder can be implemented by defining four variables: , , , and . The decoder will first compute ’s, hard estimates of ’s, where , from the LLRs obtained by adding LLRs of the output of check-node operations. For example, LLR of is computed by adding and , where denotes the LLR of . Depending on the value of ’s, additional LLRs for are obtained from . For example, additional LLR for is when and is when . After adding the additional LLRs to the received LLRs, the decoder finds hard estimates of using Wagner decoder. Finally, these hard estimates are used along with ’s to estimate .
-12 Case 11
A low-complexity decoder can be implemented by observing that constitute an (8,4) extended Hamming code, where . As such, the decoders of Case 4 for can be used to find ’s, estimates of ’s for . Then, depending on the values of , additional LLRs for are obtained from ’s, where . For example, the additional LLR for is if and otherwise. After adding the LLRs, Wagner decoder is used to compute estimates of . The decoded bits along with are then used to compute estimates of .
-13 Case 12
For the first case, , the decoder of Case 11 can be used to decode the received LLRs, with the exception that the Wagner decoder is not used at all. Rather, hard decisions are made on the updated LLRs of .
In the second case, , the code word consists of four separate (4,3) SPC codes, which can be individually decoded by the Wagner rule.
-14 Case 13
Introducing a new variable, , results in a cycle-free Tanner graph as shown in Fig. 5. As such, a non-iterative optimal MAP decoder can easily be implemented for this case.
A low-complexity decoder can also be constructed for this code. For example, making a hard decision on results in four separate SPC codes, which can be decoded by the Wagner rule.
-15 Case 14
This code consists of two (8,7) SPC codes, which can be optimally decoded by two Wagner decoders.
-16 Case 15
This is a (16,15) SPC code, and Wagner decoder can be used to decode the received LLRs optimally.
-17 Case 16
The optimal decoder will make hard decisions on the LLRs of the received bits.
The reference list from the paper itself. Each links out to its DOI / PubMed record.
- 1[1] E. Arıkan, “Channel polarization: A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels,” IEEE Trans. Inf. Theory , vol. 55, no. 7, pp. 3051–3073, Jul. 2009.
- 2[2] G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Fast polar decoders: Algorithm and implementation,” IEEE J. Sel. Areas Commun. , vol. 32, no. 5, pp. 946–957, May 2014.
- 3[3] G. Sarkis, I. Tal, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Flexible and low-complexity encoding and decoding of systematic polar codes,” IEEE Trans. Commun. , vol. 64, no. 7, pp. 2732–2745, Jul. 2016.
- 4[4] P. Giard, G. Sarkis, C. Thibeault, and W. J. Gross, “237 Gbit/s unrolled hardware polar decoder,” Electron. Lett. , vol. 51, no. 10, pp. 762–763, May 2015.
- 5[5] A. Alamdar-Yazdi and F. R. Kschischang, “A simplified successive-cancellation decoder for polar codes,” IEEE Commun. Lett. , vol. 15, no. 12, pp. 1378–1380, Dec. 2011.
- 6[6] K. Niu, K. Chen, J. Lin, and Q. T. Zhang, “Polar codes: Primary concepts and practical decoding algorithms,” IEEE Commun. Mag. , vol. 52, no. 7, pp. 192–203, Jul. 2014.
- 7[7] Huawei and Hi Silicon, “Details of the polar code design,” 3GPP TSG RAN WG 1 Meeting#87, Reno, USA, Tech. Rep. R 1-1611254, Nov. 2016.
- 8[8] Qualcomm Incorporated, “LDPC rate and compatible design overview,” 3GPP TSG-RAN WG 1 #86bis, Lisbon, Portugal, Tech. Rep. R 1-1610137, Oct. 2016.