Sparse geometries handling in lattice-Boltzmann method implementation for graphic processors

TL;DR

This paper presents a high-performance GPU implementation of the lattice-Boltzmann method for sparse geometries, utilizing a tiling approach that reduces bandwidth overhead and improves memory efficiency.

Contribution

The authors introduce a tiling-based method for LBM on GPUs that enhances performance and reduces memory usage in sparse geometries, supported by theoretical analysis and empirical results.

Findings

Achieved 682 MLUPS on GTX Titan for 3D geometries.

Tiling reduces bandwidth overhead compared to indirect addressing.

Memory reduction possible in 2D with performance trade-offs.

Abstract

We describe a high-performance implementation of the lattice-Boltzmann method (LBM) for sparse geometries on graphic processors. In our implementation we cover the whole geometry with a uniform mesh of small tiles and carry out calculations for each tile independently with a proper data synchronization at tile edges. For this method we provide both the theoretical analysis of complexity and the results for real implementations for 2D and 3D geometries. Based on the theoretical model, we show that tiles offer significantly smaller bandwidth overhead than solutions based on indirect addressing. For 2-dimensional lattice arrangements a reduction of memory usage is also possible, though at the cost of diminished performance. We reached the performance of 682 MLUPS on GTX Titan (72\% of peak theoretical memory bandwidth) for D3Q19 lattice arrangement and double precision data.