Hardware-Efficient Schemes of Quaternion Multiplying Units for 2D Discrete Quaternion Fourier Transform Processors

TL;DR

This paper presents three hardware-efficient schemes for quaternion multiplication units that significantly reduce the complexity of discrete quaternion Fourier transform processors, enabling faster and more resource-efficient implementations.

Contribution

The paper introduces three novel structural solutions for quaternion multiplication units that lower hardware complexity compared to traditional methods.

Findings

Reduced number of multipliers and adders for quaternion operations

Efficient hardware design for sq, qt, and sqt products

Potential for faster, resource-efficient quaternion Fourier transform processors

Abstract

In this paper, we offer and discuss three efficient structural solutions for the hardware-oriented implementation of discrete quaternion Fourier transform basic operations with reduced implementation complexities. The first solution: a scheme for calculating sq product, the second solution: a scheme for calculating qt product, and the third solution: a scheme for calculating sqt product, where s is a so-called i-quaternion, t is an j-quaternion, and q is an usual quaternion. The direct multiplication of two usual quaternions requires 16 real multiplications (or two-operand multipliers in the case of fully parallel hardware implementation) and 12 real additions (or binary adders). At the same time, our solutions allow to design the computation units, which consume only 6 multipliers plus 6 two input adders for implementation of sq or qt basic operations and 9 binary multipliers plus 6 two-input adders and 4 four-input adders for implementation of sqt basic operation.