A 588 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing

TL;DR

This paper presents a 588 Gbps LDPC decoder with a novel finite-alphabet message passing algorithm and serial message transfer, achieving ultra-high throughput, reduced area, and improved energy efficiency over traditional decoders.

Contribution

It introduces a finite-alphabet message passing algorithm combined with a serial message transfer architecture, significantly enhancing throughput and efficiency in LDPC decoding.

Findings

Achieves 588 Gbps throughput in LDPC decoding.

Reduces area by 3.1 times compared to min-sum decoder.

Doubles energy efficiency relative to traditional designs.

Abstract

An ultra-high throughput low-density parity check (LDPC) decoder with an unrolled full-parallel architecture is proposed, which achieves the highest decoding throughput compared to previously reported LDPC decoders in the literature. The decoder benefits from a serial message-transfer approach between the decoding stages to alleviate the well-known routing congestion problem in parallel LDPC decoders. Furthermore, a finite-alphabet message passing algorithm is employed to replace the variable node update rule of the standard min-sum decoder with look-up tables, which are designed in a way that maximizes the mutual information between decoding messages. The proposed algorithm results in an architecture with reduced bit-width messages, leading to a significantly higher decoding throughput and to a lower area as compared to a min-sum decoder when serial message-transfer is used. The architecture is placed and routed for the standard min-sum reference decoder and for the proposed finite-alphabet decoder using a custom pseudo-hierarchical backend design strategy to further alleviate routing congestions and to handle the large design. Post-layout results show that the finite-alphabet decoder with the serial message-transfer architecture achieves a throughput as large as 588 Gbps with an area of 16.2 mm$^2$ and dissipates an average power of 22.7 pJ per decoded bit in a 28 nm FD-SOI library. Compared to the reference min-sum decoder, this corresponds to 3.1 times smaller area and 2 times better energy efficiency.

Figures

Tables

Table 1. TABLE I: Critical path delays for MS and LUT-based decoder

Path	MS decoder	LUT-based decoder
CN [ns]	$2.38$	$1.42$
VN [ns]	$0.96$	$1.24$
Routing [ns]	$1.51$	$1.16$

Table 2. TABLE II: Detailed area for CN/VN unit ⋆

Component	MS decoder	LUT-based decoder
CN unit logic [$\mu m$2]	$1578$	$485$
CN unit register [$\mu m$2]	$1695$	$971$
CN macro [$\mu m$2]	$\mathrm{𝟑𝟔𝟎𝟕}$	$\mathrm{𝟏𝟓𝟏𝟎}$
VN unit logic [$\mu m$2]	$315$	${403}^{†}$
VN unit register [$\mu m$2]	$381$	${235}^{†}$
VN macro [$\mu m$2]	$\mathrm{𝟕𝟓𝟓}$	${\mathrm{𝟔𝟒𝟔}}^{†}$

Table 3. TABLE III: Power and energy efficiency comparison for MS and LUT-based decoder

	MS decoder	LUT-based decoder
Total power @ $f_{\max }$ [mW]	$12248$	$13350$
Total power @ $662$MHz [mW]	$12248$	$10257$
Leakage power [mW]	$7.44$	$5.27$
Energy efficiency [pJ/bit]	$45.2$	$22.7$

Table 4. TABLE IV: Implementation results for MS and LUT-based decoder and comparison with other works

	MS decoder	LUT-based decoder	[14]	[8]	[20]	[23]	[27]	[26]
Process technology	$28$nm FD-SOI		$65$nm CMOS	$65$nm CMOS low-power	$65$nm CMOS	$90$nm CMOS	$90$nm CMOS	$90$nm CMOS
Supply voltage [V]	$1.0$		$1.2$	$1.2$	$1.3$	$0.9$	$1.2$	$1.0$
LDPC code	$(2048,1723)$		$(672,546)$	$(2048,1723)$	$(2048,1723)$	$(2048,1723)$	$(2048,1723)$	$(2048,1723)$
Node degree ($d_v,d_c$)	$(6,32)$		$(3,6)$	$(6,32)$	$(6,32)$	$(6,32)$	$(6,32)$	$(6,32)$
Algorithm	min-sum	finite-alphabet	min-sum	offset min-sum with post processor	split-row	normalized probablistic min-sum	reduced-complexity min-sum	delayed stochastic
$I_{\text{max}}$	$5$		$9$	$8$	$11$	$9$	$30$	$-$
Quantization bits	$5$	$\mathrm{𝟑}$	$4$	$4$	$5$	$4$	$6$	$5$
$E_b/N_0$ @ BER$={10}^{-7}$ [dB]	$4.97$	$4.95$	$-$	$4.25$	$4.55$	$4.4$	$4.32$	$4.7$
Architecture	unrolled full-parallel		unrolled full-parallel	partial-parallel	full-parallel	full-parallel	full-parallel	full-parallel
Core area [mm2]	$23.3$	$16.2$	$12.9$	$5.05$	$4.84$	$9.6$	$3.84$	$3.93$
Area utilization [%]	$66.4$	$65.9$	$76$	$84.5$	$97$	$91$	$-$	$93$
Max. frequency ($f_{\max }$) [MHz]	$662$	$862$	$257$	$700$	$195$	$199.6$	$226$	$750$
Latency [ns]	$151$	$69.6$	$105$	$137$	$56.4$	$45.09$	$-$	$800$
Throughput @ $I_{\text{max}}$ [Gbps]	$271$	$\mathrm{𝟓𝟖𝟖}$	$160.8$	$\mathrm{\hspace{0.33em}13.3}$	$\mathrm{\hspace{0.33em}36.3}$	$45.42$	$12.8$	${172.4}^{\star }$
Power @ $f_{\max }$ [mW]	$12248$	$13350$	$5360$	$2800$	$1359$	$1110$	$1040$	$-$
Area eff. [Gbps/mm2]	$11.6$	$36.3$	$12.5$	$2.63$	$7.5$	$4.73$	$3.34$	$43.86$
Energy per bit @ $I_{\text{max}}$ [pJ/bit]	$45.2$	$22.7$	$33.3$	$\mathrm{\hspace{0.33em}\hspace{0.33em}210.5}$	$\mathrm{\hspace{0.33em}37.4}$	$24.44$	$81.2$	$-$
Scaled area eff.† [Gbps/mm2]	$11.6$	$36.3$	$156.4$	$32.9$	$93.8$	$157.1$	$110.9$	$1456.8$
Scaled energy per bit‡ [pJ/bit]	$45.2$	$22.7$	$10$	$63$	$9.5$	$9.4$	$17.5$	$-$

Equations

$$\big{\{}\mathbf{c}\in\{0,1\}^{N}\big{|}\boldsymbol{H}\mathbf{c}=\mathbf{0}\big{\}},$$

$$\displaystyle\mu_{n\rightarrow m}=\Phi_{v}\big{(}L_{n},\boldsymbol{\bar{\mu}}_{{\mathcal{N}}(n)\setminus m\rightarrow n}\big{)},$$

$$\bar{\mu}_{m\rightarrow n}=\Phi_{c}\big{(}\boldsymbol{\mu}_{{\mathcal{N}}(m)\setminus n\rightarrow m}\big{)}.$$

$${\hat{c}}_n={\Phi }_d(L_n,{\bar{\mathbf{\mu }}}_{\mathcal{N}(n)\to n}).$$

$$\Phi_{v}^{\mathrm{MS}}(L,\boldsymbol{\bar{\mu}}\big{)}=L+\sum_{i}\bar{\mu}_{i},$$

$$\Phi_{c}^{\mathrm{MS}}(\boldsymbol{\mu}\big{)}=\operatorname{sign}\boldsymbol{\mu}\,\min|\boldsymbol{\mu}|,$$

$${\Phi }_d^{\mathrm{MS}}(L,\bar{\mathbf{\mu }})=\frac{1}{2}\left(1-\mathrm{sign}\left(L+\sum _i{\bar{\mu }}_i\right)\right).$$

$$R_{\text{tot}}\approx N(d_v+1)Q(6I-1),$$

$$T=N{f}_{{\text{S}}_{\text{max}}},$$

$$f_{\text{S}_{\text{max}}}=\big{\{}\max\big{(}(Q_{\text{max}}T_{\text{CP},\text{route}}),\,(T_{\text{CP},\text{VN}}),\,(T_{\text{CP},\text{CN}})\big{)}\big{\}}^{-1},$$

Full text

I Introduction

Low-density parity-check (LDPC) codes have become the coding scheme of choice in high data-rate communication systems after their re-discovery in the 1990s [1], due to their excellent error correcting performance along with the availability of efficient high-throughput hardware implementations in modern CMOS technologies. LDPC codes are commonly decoded using iterative message passing (MP) algorithms in which the initial estimations of the bits are improved by a continuous exchange of messages between decoder computation nodes. Among the various MP decoding algorithms, the min-sum (MS) decoding algorithm [2] and its variants (e.g., offset MS, scaled MS) are the most common choices for hardware implementation. LDPC decoder hardware implementations traditionally start from one of these established algorithms (e.g., MS decoding), where the exchanged messages represent log likelihood ratios (LLRs). These LLRs are encoded as fixed point numbers in two’s-complement or sign-magnitude representation, using a small number of uniform quantization levels, in order to realize the message update rules with low-complexity conventional arithmetic operations.

Recently, there has been significant interest in the design of finite-alphabet decoders for LDPC codes [3, 4, 5, 6, 7]. The main idea behind finite-alphabet LDPC decoders is to start from one or multiple arbitrary message alphabets, which can be encoded with a bit-width that is acceptable from an implementation complexity perspective. The message update rules are then crafted as generic mapping functions to operate on this alphabet. The main advantage of such finite-alphabet decoders is that the message bit-width can be reduced significantly with respect to a conventional decoder, while maintaining the same error-correcting performance [5, 6]. The downside of this approach is that the message update rules of finite-alphabet decoders usually cannot be described using fast and area-efficient standard arithmetic circuits.

Different hardware architectures for LDPC decoders have been proposed in the literature in order to fulfill the power and throughput requirements of various standards. More specifically, various degrees of resource sharing result in flexible decoders with different area requirements. On the one hand, partial-parallel LDPC decoders [8, 9] and block-parallel LDPC decoders [10, 11] are designed for medium throughput, with modest silicon area. Full-parallel [12, 13] and unrolled LDPC decoders [14, 5], on the other hand, achieve very high throughput (in the order of several tens or hundreds of Gbps) at the expense of large area requirements. Even though, in principle, LDPC decoders are massively parallelizable, the implementation of ultra-high speed LDPC decoders still remains a challenge, especially for long LDPC codes with large node degrees [15]. While synthesis results for such long-length codes, as for example reported in [16], show the potential for a very high throughput, the actual implementation requires several further considerations mainly due to severe routing problems and the impact of parasitic effects.

Contributions

In this paper, we propose an unrolled full-parallel architecture based on serial transfer of the decoding messages, which enables an ultra-high throughput implementation of LDPC decoders for codes with large node degrees by reducing the required interconnect wires for such decoders. Moreover, we employ a finite-alphabet LDPC decoding algorithm in order to decrease the required quantization bit-width, and thus, to increase the throughput, which is limited by the serial message-transfer in the proposed architecture. We also adopt a linear floorplan for the unrolled full-parallel architecture as well as an efficient pseudo-hierarchical flow that allow the high-speed physical implementation of the proposed decoder. To the best of our knowledge, by combining the aforementioned techniques, we present the fastest fully placed and routed LDPC decoder in the literature.

Outline

The remainder of this paper is organized as follows: Section II gives an introduction to decoding of LDPC codes, as well as more details on existing high-throughput implementations of LDPC decoders. Section III describes our proposed ultra-high throughout decoder architecture that employs a serial message-transfer technique. In Section IV, our algorithm to design a finite-alphabet decoder with non-uniform quantization is explained and applied to the serial message-transfer decoder of Section III. Section V describes our proposed approach for the physical implementation and the timing and area optimization of our serial message-transfer decoders. Finally, Section VI analyzes the implementation results, and Section VII concludes the paper.

II Background

In this section, we first briefly summarize the fundamentals of LDPC codes and the iterative MP algorithm for the decoding. We then review the state-of-the-art in high speed LDPC decoder architectures to set the stage for the description of our implementation.

II-A LDPC Codes and Decoding Algorithms

A binary LDPC code is a set of codewords which are defined through an $M\times N$ binary-valued sparse parity check matrix as:

[TABLE]

where all operations are performed modulo $2$. If the parity check matrix contains exactly $d_{v}$ ones per column and exactly $d_{c}$ ones per row, the code is called a $(d_{v},d_{c})$-regular LDPC code. Such codes are usually represented with a Tanner graph, which contains $N$ variable nodes (VNs) and $M$ check nodes (CNs) and VN $n$ is connected to CN $m$ if and only if $\boldsymbol{H}_{mn}~{}=~{}1$.

LDPC codes are traditionally decoded using MP algorithms, where information is exchanged as messages between the VNs and the CNs over the course of several decoding iterations. At each iteration the message from VN $n$ to CN $m$ is computed using a mapping $\Phi_{v}:\mathbb{R}^{d_{v}}\rightarrow\mathbb{R}$, which is defined as:

[TABLE]

where $\mathcal{N}(n)$ denotes the neighbors of node $n$ in the Tanner graph, $\boldsymbol{\bar{\mu}}_{{\mathcal{N}}(n)\setminus m\rightarrow n}\in\mathbb{R}^{d_{v}-1}$ is a vector that contains the incoming messages from all neighboring CNs except $m$, and $L_{n}\in\mathbb{R}$ denotes the channel LLR corresponding to VN $n$. Similarly, the CN-to-VN messages are computed using a mapping $\Phi_{c}:\mathbb{R}^{d_{c}-1}\rightarrow\mathbb{R}$, which is defined as:

[TABLE]

Fig. 1 illustrates the message updates in the Tanner graph. In addition to $\Phi_{v}$ and $\Phi_{c}$, a third mapping $\Phi_{d}:\mathbb{R}^{d_{v}+1}\rightarrow\{0,1\}$ is needed to provide an estimate of the transmitted codeword bits in the last VN iteration based on the incoming CN messages and the channel LLR $L_{n}$ according to:

[TABLE]

Messages are exchanged until a valid codeword has been decoded or until the maximum number of iterations $I$ has been reached.

For the widely used MS algorithm, the mappings (2) and (3) are:

[TABLE]

and,

[TABLE]

where $\min|\boldsymbol{\mu}|$ denotes the minimum of the absolute values of the vector components and $\operatorname{sign}\boldsymbol{\mu}=\prod_{j}\operatorname{sign}\mu_{j}$. The decision mapping $\Phi_{d}$ is defined as:

[TABLE]

II-B High Throughput LDPC Decoders

Several high throughput LDPC decoders have been developed during the past decade in order to satisfy the high data-rate requirements of optical and high-speed Ethernet networks. These decoders usually rely on a full-parallel isomorphic [17] architecture and a flooding schedule, which directly maps the algorithm for one iteration to hardware. More specifically, the CN and VN update equations are directly mapped to $M$ CN and $N$ VN processing units and a hard-wired routing network is responsible for passing the messages between them. From an implementation perspective, while such an architecture enables a very high throughput by fully exploiting the inherent parallelism of each iteration, the complexity of the highly unstructured routing network turns out to be a severe bottleneck. In addition to this routing problem, such full-parallel decoders usually require one or two clock cycles for each iteration and in the worst case as many cycles as the maximum number of iterations for each codeword, which is another throughput limitation factor.

Several solutions have been proposed to alleviate the routing problem in full-parallel decoders, on both architectural and algorithmic levels. The authors of [18, 19] suggest using a bit-serial architecture, which only requires a single wire for each variable-to-check and check-to-variable node connection. While this approach can reduce the routing congestion, it also leads to a significant reduction in the decoding throughput. The decoder in [19], for example, only achieves a throughput of $3.3$ Gbps when implemented using a $130$ nm CMOS technology. Another architectural technique is reported in [13], where the long wires of the decoder are partitioned into several short wires with pipeline registers. As a result, the critical path is broken down into shorter paths, but the decoder throughput is also affected since more cycles are required to accomplish each iteration. Nevertheless, the decoder of [13] is still able to achieve $13.2$ Gbps in $90$ nm CMOS with $16$ iterations.

On an algorithmic level, the authors of [20] propose a MP algorithm, called MS* split-row threshold*, which uses a column-wise division of the $\boldsymbol{H}$ matrix into $S_{pn}$ partitions. Each partition contains $N/S_{pn}$ VNs and $M$ CNs, and global interconnects are minimized by only sharing the minimum signs between the CNs of each partition. This algorithmic modification was used to implement a full-parallel decoder for the challenging $(2048,1723)$ LDPC code in $65$ nm CMOS, which achieves a throughput of $36.2$ Gbps with $11$ decoding iterations. Another decoder, reported in [21], uses a hybrid hard/soft decoding algorithm, called differential binary MP algorithm, which reduces the interconnect complexity at the cost of some error-correcting performance degradation. A full-parallel $(2048,1723)$ LDPC decoder using this algorithm was implemented in $65$ nm CMOS technology, achieving a throughput of up to $126$ Gbps [22]. The work of [23] also proposes another algorithmic level modification, called the probabilistic MS algorithm, where a probabilistic second minimum value is used instead of the true second minimum value to simplify the CN operation and to facilitate high-throughput implementation of full-parallel LDPC decoders. Further, a mix of tree and butterfly interconnect network is proposed in the CN unit to balance the interconnect complexity and the logic overhead and to reduce the routing complexity. The implementation of a decoder for the $(2048,1723)$ LDPC code with the proposed techniques in $90$ nm CMOS technology achieves a throughput of $45.42$ Gbps.

Stochastic decoding of LDPC codes [24] was another important improvement based on both algorithm and gate-level implementation considerations to solve the routing problem of LDPC decoders, where probabilities are interpreted as binary Bernoulli sequences. This approach, on the one hand, reduces the complexity of CNs and the routing overhead, but, on the other hand, introduces difficulties in VN update rules due to correlated stochastic streams, which may deteriorate the error-correcting performance especially in longer-length codes. To solve this correlation problem by re-randomizing the VN output streams, the work of [25] proposes to use majority-based tracking forecast memories in each VN, which results in a decoder with full-parallel architecture for a $(2048,1723)$ LDPC code that achieves a throughput of $61.3$ Gbps in $90$ nm CMOS. An alternative method to track the probability values, called delayed stochastic decoding, is reported in [26] and the full-parallel decoder for the same code can deliver a throughput as large as $172.4$ Gbps in $90$ nm CMOS.

To solve the problem of throughput limitations in full-parallel decoders from potentially using multiple iterations for decoding, the work of [14] presents an unrolled full-parallel LDPC decoder. In the proposed architecture, each decoding iteration is mapped to distinct hardware resources, leading to a decoder with $I$ iterations that can decode one codeword per clock cycle, at the cost of significantly increased area requirements with respect to non-unrolled full-parallel decoders. This unrolled architecture achieves a throughput of $161$ Gbps for a $(672,546)$ LDPC code with $d_{v}=3$ and $d_{c}=6$, when implemented in a $65$ nm CMOS technology. It is noteworthy that an unrolled decoder has $50\%$ reduced wires between adjacent stages compared to a non-unrolled decoder since one stage of variable nodes is connected to one stage of check nodes with uni-directional data flow per decoding iteration. Even though this measure leads to a lower routing congestion, it is still challenging to fully place and route such a decoder. This routing issue becomes more and more severe when considering longer LDPC codes and especially with increasing CN and VN degrees to achieve better error-correcting performance, as required in wireline applications such as for the $(2048,1723)$ code with $d_{v}=6$ and $d_{c}=32$ used in the IEEE 802.3an standard [15].

III Serial Message-Transfer LDPC Decoder

Unrolled full-parallel LDPC decoders provide the ultimate throughput with smaller routing congestion than conventional full-parallel decoders. However, they are still not trivial to implement for long LDPC codes with high CN and VN degrees, which suffer from severe routing congestion. Hence, in this section, we propose an unrolled full-parallel LDPC decoder architecture that employs a serial message-transfer technique between CNs and VNs.111We note that a first implementation of our decoder was based on parallel (word-level) message-transfer. The place and route tool for this implementation was hardly able to converge even when the area utilization was unacceptable. We, therefore, propose serial message-transfer architecture and we adopt special implementation methodologies for this architecture, which will be explained in Section V. This architecture is similar to the bit-serial implementations of [18, 19] in the way the messages are transferred; however, as we shall see later, it differs in the fact that it is unrolled and in the way the messages are processed in the CNs and VNs.

III-A Decoder Architecture Overview

An overview of the proposed unrolled serial message-transfer LDPC decoder architecture is shown in Fig. 2. As with all unrolled LDPC decoders, each decoding iteration is mapped to a distinct set of $N$ VN and $M$ CN units, which form a processing pipeline. In essence, the unrolled LDPC decoder is a systolic array, in which a new set of $N$ channel LLRs is read in every clock cycle and a decoded codeword is put out in every clock cycle.

Even though both the CNs and VNs can compute their outgoing messages in a single clock cycle, similar to the architecture in [5], in the proposed serial message-transfer architecture each message is transfered one bit at a time between the consecutive variable node and check node stages over the course of $Q_{\text{msg}}$ clock cycles, where $Q_{\text{msg}}$ is the number of bits used for the messages. More specifically, each CN and VN unit contains a serial-to-parallel (S/P) and parallel-to-serial (P/S) conversion unit at the input and output, respectively, which are clocked $Q_{\text{msg}}$ times faster than the processing clock to collect and transfer messages serially, while keeping the overall decoding throughput constant. More details on the architecture of the CN and VN units as well as the proposed serial message-transfer mechanism are provided in the sequel.

III-B Decoder Stages

The unrolled LDPC decoder, illustrated in Fig. 2, consists of three types of processing stages, which are described in more detail below. We note that the CN/VN processors of this reference decoder are similar to those of a standard MS decoder, and our modifications for these parts (to realize a finite-alphabet decoder) are discussed in Section IV.

III-B1 Check Node Stage

Each check node stage consists of $M$ CN units, each of which contains three components: a CN processor, which implements (6) similarly to [5, 14], $d_{c}$ S/P units for the $d_{c}$ input messages, and $d_{c}$ P/S units for the $d_{c}$ output messages. Moreover, the complete check node stage contains a register bank that is used to store the channel LLRs, which are not directly needed by the check node stage, but nevertheless must be forwarded to the following variable node stage and thus need to be buffered. Hence, no S/P and P/S units are required for the channel LLR buffers in the check node stages as they are simply forwarded serially to the following variable node stage.

III-B2 Variable Node Stage

Each variable node stage consists of $N$ VN units, each of which contains a VN processor and S/P and P/S units at the inputs and outputs, respectively, similar to the CN unit structure. Each VN processor implements the update rule (5) similarly to [5].

III-B3 Decision Node Stage

The last variable node stage is called a decision node stage because it is responsible for taking the final hard decisions on the decoded codeword bits. The structure of this stage is similar to a variable node stage, but a decision node (DN) has a simpler version of the VN processor that only computes sum of all inputs and put out its sign [5], and thus no P/S unit is required at its output.

III-C Message Transfer Mechanism

One of the modifications, compared to [14] and [5], is the serial transfer of the channel and message LLRs between the stages of the decoder, which reduces the required routing resources by factor of $Q_{\text{msg}}$. This modification is applied to make the placement and routing of the decoder feasible, especially for large values of $d_{v}$ and $d_{c}$. To this end, as explained in the previous section, a S/P and a P/S shift register are added to each input and each output of the CN and VN units, as illustrated in Fig. 3. We see that the S/P unit consists of a ($Q_{\text{msg}}-$1)-bit shift register and $Q_{\text{msg}}$ memory registers, while the P/S unit has $Q_{\text{msg}}$ registers with multiplexed inputs. The serial messages are transfered with a fast clock, denoted by CLK${}_{\text{F}}$, that is $Q_{\text{msg}}$ times faster than the slow processing clock, denoted by CLK${}_{\text{S}}$. More specifically, at each CN unit and VN unit input, data is loaded serially into the S/P shift register using the fast CLK${}_{\text{F}}$, and after the $Q_{\text{msg}}$-th cycle all message bits are stored in memory registers, clocked by the slow CLK${}_{\text{S}}$. The CN/VN processing can then be performed in one CLK${}_{\text{S}}$ cycle and the output messages are saved in the output P/S shift register and transferred serially to the next stage using again CLK${}_{\text{F}}$. At the same time, a new set of messages is serially loaded into the input shift register. We note that for simpler clock tree generation, all registers in Fig. 3 are clocked by CLK${}_{\text{F}}$, while CLK${}_{\text{S}}$ is actually implemented as a pulsed clock, which is generated using a clock-gating cell controlled by a finite state machine.

III-D Decoder Hardware Complexity and Performance Analysis

In this section, we describe the required memory complexity of the proposed decoder as well as the decoding latency and the throughput.

III-D1 Memory Requirement

The memory complexity can easily be characterized by counting the number of required registers and can be approximated by:

[TABLE]

where $I$ is the number of decoding iterations (which in unrolled decoders strongly affects the memory requirements) and $Q=Q_{\text{msg}}=Q_{\text{ch}}$, which is often the case for MS LDPC decoders. From (8), one can easily see that the quantization bit-width linearly increases the memory requirement for the proposed architecture.

III-D2 Decoding Latency

Since each stage has a delay of two CLK${}_{\text{S}}$ cycles and there are two stages for each decoding iteration, the decoder latency is $4I$ CLK${}_{\text{S}}$ cycles or, equivalently, $4IQ_{\text{max}}$ CLK${}_{\text{F}}$ cycles, where $Q_{\text{max}}=\max(Q_{\text{msg}},Q_{\text{ch}})$.

III-D3 Decoding Throughput

In the proposed unrolled architecture, one decoder codeword is output in each CLK${}_{\text{S}}$ cycle. Therefore, the coded throughput of the decoder is:

[TABLE]

where $f_{\text{S}_{\text{max}}}$ is the maximum frequency of CLK${}_{\text{S}}$ while the maximum frequency of CLK${}_{\text{F}}$ or simply maximum frequency of the decoder is $f_{\text{max}}=f_{\text{F}_{\text{max}}}=Q_{\text{max}}f_{\text{S}_{\text{max}}}$. For the proposed architecture, we have:

[TABLE]

where $T_{\text{CP},\text{VN}}$ and $T_{\text{CP},\text{CN}}$ are the delay of the critical paths of the CN unit and the VN unit, respectively, and $T_{\text{CP},\text{route}}$ is the critical path delay of the (serial) routing between the decoding stages. Thus, the decoder throughput will be limited by the routing, if the VN/CN delay is smaller than $Q_{\text{max}}$ times the routing delay. Hence, on the one hand, the serial message-transfer decoder alleviates the routing problem by reducing the required number of wires, but on the other hand, the decoder throughput for large quantization bit-widths may be affected, as the serial message-transfer delay will become the limiting factor.

IV Finite-Alphabet Serial Message-Transfer LDPC Decoder

Even though the serial message-transfer architecture alleviates the routing congestion of an unrolled full-parallel LDPC decoder, it has a negative impact on both throughput and hardware complexity, as discussed in the previous section. In our previous work [6, 5], we have shown that finite-alphabet decoders have the potential to reduce the required number of message bits while maintaining the same error rate performance. In this section, we will review the basic idea and our design method for this new type of decoders and then show how the bit-width reduction technique of [6, 5] can be applied verbatim in order to increase the throughput and reduce the area of the serial message-transfer architecture.

IV-A Mutual Information Based Finite-Alphabet Decoder

In our approach of [5, 6], the standard message-passing decoding algorithm update rules are replaced by custom update rules that can be implemented as simple look-up tables (LUTs). These LUTs take integer-valued input messages and produce a corresponding output message. Moreover, the input-output mapping that is represented by the LUTs is designed in a way that maximizes the mutual information between the LUT output messages and the codeword bit that these messages correspond to. We note that a similar approach was also used in [7], but the corresponding hardware implementation would have a much higher hardware complexity than the method of [5, 6]. This happens because, contrary to [7], in [5, 6] we used LUTs only for the VNs while the CNs use the standard min-sum update rule.

IV-B Error-Correcting Performance and Bit-Width Reduction

In Fig. 4, we compare the performance of the IEEE 802.3an LDPC code under floating-point MS decoding, fixed-point MS decoding (with $Q_{\text{ch}}=Q_{\text{msg}}\in\{4,5\}$), and LUT-based decoding (with $Q_{\text{ch}}=4$ and $Q_{\text{msg}}=3$) when performing $I=5$ decoding iterations with a flooding schedule. We also show the performance of a floating-point offset min-sum (OMS) decoder as a reference.222The reference simulation was obtained and matched with our simulation by using the open-source simulator provided by: Adrien Cassagne; Romain Tajan; Mathieu Léonardon; Baptiste Petit; Guillaume Delbergue; Thibaud Tonnellier; Camille Leroux; Olivier Hartmann, “AFF3CT: A Fast Forward Error Correction Tool,” 2016. [Online]. Available: https://doi.org/10.5281/zenodo.167837 We observe that the fixed-point decoder with $Q_{\text{ch}}=Q_{\text{msg}}=5$ has almost the same performance as the floating-point decoder, while the fixed-point decoder with $Q_{\text{ch}}=Q_{\text{msg}}=4$ shows a significant loss with respect to the floating-point implementation. Thus, a standard MS decoder would need to use at least $Q_{\text{ch}}=Q_{\text{msg}}=5$ quantization bits. The LUT-based decoder, however, can match the performance of the floating-point decoder with only $Q_{\text{ch}}=4$ channel quantization bits and $Q_{\text{msg}}=3$ message quantization bits.333We note that reducing $Q_{\text{ch}}$ further results in a non-negligible loss with respect to the floating-point decoder. Additionally, with the above quantization bit choices, no noticeable error floor has been observed for both the MS decoder and LUT-based decoder when $10^{10}$ frames have been transmitted (which corresponds to a BER $\approx 10^{-12}$ with the current block length). We note that, for the LUT-based decoder, the performance in the error floor region can be traded with the performance in the waterfall region by an appropriate choice of the design SNR for the LUTs [6].

IV-C LUT-Based Decoder Hardware Architecture

The LUT-based serial message-transfer decoder hardware architecture is very similar to the MS decoder architecture, described in Section III. However, the LUT-based decoder can take advantage of the significantly fewer message bits that need to be transferred from one decoding stage to the next. This reduction reduces the number of CLK${}_{\text{F}}$ cycles per iteration, which in turn increases the throughput of the decoder according to (10) provided that the CN/VN logic is sufficiently fast. Moreover, the size of the buffers needed for the S/P and P/S conversions is also reduced significantly, which directly reduces the memory complexity of the decoder (see (8)).

On the negative side, we remark that the VN units for each variable node stage (decoder iteration) of the LUT-based decoder are different, which slightly complicates the hierarchical physical implementation as we will see later. Furthermore, since $Q_{\text{ch}}>Q_{\text{msg}}$, we now need to transfer the channel LLRs with multiple (two) bits per cycle to avoid the need to artificially limit the number of CLK${}_{\text{F}}$ cycles per iteration to $Q_{\text{ch}}$ rather than to the smaller $Q_{\text{msg}}$. To reflect this modification, we redefine (10) as $Q_{\text{max}}=\max(Q_{\text{msg}},\lceil\frac{Q_{\text{ch}}}{2}\rceil)$. While this partially parallel transfer of the channel LLRs impacts routing congestion, we note that the overhead is negligible since the number of channel LLRs is small compared to the total number of messages.

V Implementation

Despite the use of a serial message-transfer, the physical implementation of the decoders proposed in the previous sections requires special scrutiny since the number of global wires is still significant and the overall area is particularly large. Therefore, in this section, we propose and describe a pseudo-hierarchical design methodology to implement the serial message-transfer architecture.

V-A Physical Design

Due to the large number of identical blocks in the decoder architecture, a bottom-up flow is expected to provide the best results. The CN, VN, and DN units are first placed and routed individually to build hard macros,444Note that for the LUT-based decoder there are different macros for each variable node stage as apposed to the MS decoder. and their timing and physical information are extracted. These macros are then instantiated as large cells in the decoder top level. We propose to treat the macros as custom standard-cells with identical height to be able to perform the placement using the standard-cell placement, rather than the less capable macro placement of the backend tool, since in our case the number of hard macro instances is extremely large and the interconnect pattern is complex and highly irregular.

Fig. 5 illustrates the proposed physical floorplan for the decoders with the unrolled architecture. In this floorplan, the CN and VN macros within each stage are constrained to be placed into dedicated regions (placement regions in Fig. 5a). This measure enforces the high-level structure of systolic array pipeline, but it also leaves freedom to the placement tool to choose the location for the macros in each stage to minimize routing congestion between stages. Note that the linear floorplan has also the advantage of being scalable in the number of iterations since little interaction or interference exists between stages. Furthermore, the CN and VN macros are placed in dedicated rows while the area between these rows is left for repeaters and for the register standard-cells for the channel LLRs in the check node stages, as shown in Fig. 5b. We note that the proposed floorplan and the encapsulation of the VN and CN macros as large standard-cells exploit the automated algorithm to optimize both custom and conventional standard-cells placement in order to alleviate the significant routing congestion.

V-B Timing and Area Optimization Flow

Although the synthesis results can give an approximate evaluation for timing and area of the physical implementation, several iterations with different constraints are required to reach an optimal layout. To this end, we propose the methodology illustrated in the flowchart of Fig. 6 to effectively implement the serial message-transfer architecture. The main idea behind this methodology is that three main factors directly contribute to the decoder throughput and also indirectly to the decoder area, as discussed in Section III and specifically summarized in (10). Our goal is to maximize the throughput at a minimum area.

We define the timing constraint applied to CLK${}_{\text{S}}$ as $T_{\text{CSTR},\text{CLK}_{\text{S}}}$, and the timing constrain applied to CLK${}_{\text{F}}$ as $T_{\text{CSTR},\text{CLK}_{\text{F}}}$. The first step is to place and route the CN/VN macros based on $T_{\text{CSTR},\text{CLK}_{\text{S}}}$. This step is followed by the implementation of the decoder using $T_{\text{CSTR},\text{CLK}_{\text{F}}}$. (The initial constraints for the backend are thereby extracted from synthesis timing results.) The fully placed and routed design can give an accurate routing delay, which will be used to update $T_{\text{CSTR},\text{CLK}_{\text{F}}}$ and then $T_{\text{CSTR},\text{CLK}_{\text{S}}}$ according to (10). The updated $T_{\text{CSTR},\text{CLK}_{\text{S}}}$ will be used to re-implement the CN and VN macros within the minimum achievable area.

We note that for a long LDPC code with a large area and long routing delay (such as the one of the IEEE 802.3an standard), the first implementation starts with $T_{\text{CSTR},\text{CLK}_{\text{S}}}$ <Q_{\text{max}}$$T_{\text{CSTR},\text{CLK}_{\text{F}}}. After obtaining a realistic value for the CLK${}_{\text{F}}$ period (and hence for $T_{\text{CSTR},\text{CLK}_{\text{F}}}$) at the end of the implementation, the $T_{\text{CSTR},\text{CLK}_{\text{S}}}$ will be updated to a larger value to approach $T_{\text{CSTR},\text{CLK}_{\text{S}}}$ \approx Q_{\text{max}}$$T_{\text{CSTR},\text{CLK}_{\text{F}}}. Consequently, the CN and VN macro area and thus the decoder area will shrink in the second iteration, which result in larger achievable CLK${}_{\text{F}}$ frequency and hence smaller $T_{\text{CSTR},\text{CLK}_{\text{F}}}$ and $T_{\text{CSTR},\text{CLK}_{\text{S}}}$. The feedback loop will reach the optimum point after a few iterations.

VI Results and Discussions

To study the impact of the serial message-transfer architecture and the finite-alphabet decoding scheme, we have implemented the proposed architecture by employing the methodology explained in Section V and we analyzed the results for both MS and LUT-based decoding. We used the parity check matrix of the LDPC code defined in the IEEE 802.3an standard [15], i.e., a $(2048,1723)$ LDPC code of $R=0.8413$ with $d_{v}=6$ and $d_{c}=32$. We used $I=5$ for both decoders and $Q_{\text{msg}}=Q_{\text{ch}}=5$ for the MS decoder and $Q_{\text{msg}}=3$ and $Q_{\text{ch}}=4$ for the LUT-based decoder to achieve the same error-correction performance, as described in Section IV. The decoders were synthesized from a VHDL description using Synopsys Design Compiler and placed and routed using Cadence Encounter Digital Implementation. The layouts are shown in Fig. 7. The results are reported for a $28\,$nm FD-SOI library under typical operating conditions ($V_{\mathrm{DD}}=1\,$V, $T=25^{\circ}\,$C).

VI-A Delay Analysis

In the serial message-transfer architecture, the critical path and, hence, the maximum decoding frequency are defined by (10). To investigate the impact of serially transferring the messages on the decoder throughput, we consider the delay of the following register-to-register critical paths for both the MS and LUT-based decoder.

VI-A1 CN Critical Path

The CN critical path ($T_{\text{CP},\text{CN}}$) is the path from the S/P memory registers to the P/S shift register within the CN unit. For both decoders, this path is essentially comprised of the logic cells for a sorter tree with a depth of four.

VI-A2 VN Critical Path

The VN critical path ($T_{\text{CP},\text{VN}}$) is the path from S/P memory registers to P/S shift register within the VN unit. This path is dominated by an adder tree for the MS decoder and an LUT tree for the LUT-based decoder.

VI-A3 Routing Critical Path

The routing critical path ($T_{\text{CP},\text{route}}$) comprises mainly the interconnect wires (and buffers) that connect the CN/VN unit S/P shift register to the VN/CN unit P/S shift register.

Table I summarizes the critical path delays of the CN/VN and the routing path. Together with (10), the values in the table dictate the maximum achievable frequency for CLK${}_{\text{S}}$ and CLK${}_{\text{F}}$, respectively, for both of the decoders with the proposed serial message-transfer architecture. We note that the critical paths are reported after the timing and area constraints for the CN/VN macros and for the decoder toplevel are jointly optimized according to the flow shown in Fig. 6. According to (10), we observe that in both decoders the message transfer limits the slow clock CLK${}_{\text{S}}$ to a period of $5\times 1.51\,\text{ns}=7.55\,$ns and $3\times 1.16\,\text{ns}=3.48\,$ns for the MS and the LUT-based decoder, respectively, where $1.51\,$ns and $1.16\,$ns are the corresponding minimum CLK${}_{\text{F}}$ periods. Consequently, in our flow, the VN and CN units end up as optimized for minimum area only with relaxed and easy to meet timing constraints.

VI-B Area Analysis

Fig. 8 illustrates the area distribution among the various components after the layout. The area utilization is approximately $67$% for both decoders. While almost $62$% of the layout is filled with CN/VN macros and registers, the clock tree and routing buffers occupy around $5$%. Furthermore, we see a $44$% difference in total area between the decoders due to the fact that the total area for CN and VN macros is $14.12\,$mm2 in the MS decoder, as opposed to only $9.56\,$mm2 in the LUT-based decoder.

To understand this fact, we list the area of each CN/VN macro in Table II. According to this table, the finite-alphabet message passing algorithm leads to significantly smaller CN processors because of two important factors: first, the bit-width reduction of the messages directly affects the data-path area, and second, the quantized messages in the LUT-based decoder are processed directly in the sorter tree of the CNs without the need to compute their absolute values. However, VN processors are less area-efficient in the LUT-based decoder in comparison with the ones of the MS decoder. This is caused by the fact that the LUT-based computations are, in general, less area-efficient than the conventional arithmetic based update rules. Thus, the logic area of the VN in the LUT-based decoder is larger, even though their input/output bit-width is smaller. Another contributing factor in the Table II is the register area, which is defined by the number of S/P and P/S registers. For those, the $40$% reduction of bit-width in the LUT-based decoder is directly noticeable in the register area for both CN and VN units. Altogether, the CN and VN macros in the LUT-based decoder are $58$% and $14$% smaller, respectively, compared to those of the MS decoder.

VI-C Power Analysis

The energy which is consumed by each decoder is proportional to the capacitance, which in turn is related to the decoder area. Also, the number of required CLK${}_{\text{F}}$ cycles for the serial message-transfer to decode one codeword, which is inversely proportional to the decoding throughput at a constant frequency, directly contributes to the consumed energy for each decoded bit. Therefore, we analyze both the total power and the energy efficiency of the decoders using post-layout vector-based power analysis.555We first extract the parasitic information of both the hard macros and the top level from the placement and routing tool and then read and link them using a power computation tool to generate the complete parasitic information. The results are reported in Table III. We note that the total powers are calculated at $f_{\text{max}}$ for both decoders. Also, for comparison purpose, we have calculated the total powers at a constant CLK${}_{\text{F}}$ frequency, here $\min(f_{\text{max},\text{MS}},f_{\text{max},\text{LUT}})=662\,$MHz, for both decoders and note them in the Table III. According to this table, the total power consumption of the LUT-based decoder is $16.2$% smaller than that of the MS decoder. Furthermore, by considering the fact that the LUT-based decoder has $66.7$% higher throughput than the MS decoder at a similar CLK${}_{\text{F}}$ frequency, the energy efficiency of the LUT-based decoder is almost $2$ times better in comparison with the MS decoder.

VI-D Summary and Final Comparison

The final post-layout results for our MS and LUT-based decoders and also for some other recently implemented decoders are summarized in Table IV. Our LUT-based decoder runs at a maximum CLK${}_{\text{F}}$ frequency of $f_{\text{max},\text{LUT}}=862\,$MHz and delivers a sustained throughput of $588\,$Gbps, while it occupies $16.2\,$mm2 area and dissipates $22.7\,$pJ/bit. Compared to the MS decoder, the LUT-based decoder is 1.4$$\times smaller, 2.2$$\times faster, and thus 3.1$$\times more area efficient. It also has $16.2$% lower power dissipation and 2$$\times better energy efficiency, when the decoding throughout is taken into account.

The work in [14] is the only other unrolled full-parallel decoder in literature, but it is designed for the IEEE 802.11ad [28] code, which has a shorter block length and smaller node degrees ($d_{v}=3$ and $d_{c}=6$ as opposed to $d_{v}=6$ and $d_{c}=32$ for the code used in the design reported in this paper). The work of [8], [20, 26, 23], and [27] are for the same IEEE 802.3an code considered in this paper, but with partial-parallel and full-parallel architectures. The proposed LUT-based decoder has more than an order of magnitude higher throughput compared to [20] and [23], and three times higher throughput compared to [26], while the maximum throughput of the proposed decoder is maintained for all SNR scenarios as it does not require early termination to achieve a high throughput. The area efficiency of the proposed unrolled full-parallel architecture, however, is inferior to the one of the decoders in [20, 23] and [27] with full-parallel architecture due to the repeated routing overhead between the decoder stages in our design.

VII Conclusion

An ultra high throughput LDPC decoder with a serial message-transfer architecture and based on non-uniform quantization of messages was proposed to achieve the highest decoding throughput in literature. The proposed decoder architecture is an unrolled full-parallel architecture with serialized messages for CN/VN units, which was enabled by employing S/P and P/S shift registers at the inputs and outputs of each unit. The proposed quantized message passing algorithm replaces conventional MS, resulting in $40$% reduction in message bit-width without any performance penalty. This algorithm was implemented by using generic LUTs instead of adders for VNs while the CNs remained unchanged compared to MS decoding. Placement and routing results in $28\,$nm FD-SOI show that the LUT-based serial message-transfer decoder delivers $0.588\,$Tbps throughput and is $3.1$ times more area efficient and $2$ times more energy efficient in comparison with the MS decoder with serial message-transfer architecture.

Acknowledgment

This work was supported by the Swiss National Science Foundation (SNSF) under the project number 200021-153640.