A Study of Complex Deep Learning Networks on High Performance, Neuromorphic, and Quantum Computers

TL;DR

This paper explores combining quantum, high performance, and neuromorphic computing to overcome key limitations of traditional deep learning models, enabling complex, optimized, and low-power neural network implementations.

Contribution

It demonstrates the feasibility of using three advanced architectures together to enhance deep learning, addressing topology complexity, manual configuration, and power efficiency.

Findings

Quantum computing can optimize intra-layer weights efficiently.

HPC can determine optimal network topologies automatically.

Neuromorphic hardware can implement complex networks with low power.

Abstract

Current Deep Learning approaches have been very successful using convolutional neural networks (CNN) trained on large graphical processing units (GPU)-based computers. Three limitations of this approach are: 1) they are based on a simple layered network topology, i.e., highly connected layers, without intra-layer connections; 2) the networks are manually configured to achieve optimal results, and 3) the implementation of neuron model is expensive in both cost and power. In this paper, we evaluate deep learning models using three different computing architectures to address these problems: quantum computing to train complex topologies, high performance computing (HPC) to automatically determine network topology, and neuromorphic computing for a low-power hardware implementation. We use the MNIST dataset for our experiment, due to input size limitations of current quantum computers. Our results show the feasibility of using the three architectures in tandem to address the above deep learning limitations. We show a quantum computer can find high quality values of intra-layer connections weights, in a tractable time as the complexity of the network increases; a high performance computer can find optimal layer-based topologies; and a neuromorphic computer can represent the complex topology and weights derived from the other architectures in low power memristive hardware.