# A high-resolution programmable Vernier delay generator based on carry chains in FPGA

## TL;DR

This paper introduces a high-resolution, resource-efficient FPGA-based Vernier delay generator utilizing carry chains, achieving 38.6 ps resolution with high linearity for use in precise physical instruments.

## Contribution

It presents a novel FPGA delay generator architecture with combined coarse and fine delay steps using carry chains organized in a Vernier loop, demonstrating high resolution and linearity.

## Key findings

- Resolution of 38.6 ps achieved
- DNL and INL within ±0.24 LSB
- Resource usage is minimal with 668 LUTs and 146 registers

## Abstract

This paper presents an architecture of high-resolution delay generator implemented in a single field programmable gate array (FPGA) chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show the obtained resolution is 38.6 ps, and the differential nonlinearity (DNL) and integral nonlinearity (INL) is in the range of (-0.18 least significant bit (LSB),0.24 LSB)\(-0.02 LSB,0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 20 degrees centigrade. The delay generator is also rather resource cost efficient which uses only 668 LUTs and 146 registers in total.