Parallelization of Path Planning Algorithms for AUVs Concepts, Opportunities, and Program-Technical Implementation

TL;DR

This paper demonstrates that energy-efficient, many-core computing architectures like the SCC can enable onboard, computation-intensive path planning for battery-powered AUVs, enhancing autonomous underwater operations.

Contribution

It presents a case study porting a path planning algorithm onto a 48-core SCC, analyzing performance, power, and energy consumption for AUV applications.

Findings

Path planning can be effectively executed onboard AUVs.

Energy-aware architectures improve power efficiency for intensive tasks.

Future deployment planned on a real glider.

Abstract

Modern autonomous underwater vehicles (AUVs) have advanced sensing capabilities including sonar, cameras, acoustic communication, and diverse bio-sensors. Instead of just sensing its environment and storing the data for post-Mission inspection, an AUV could use the collected information to gain an understanding of its environment, and based on this understanding autonomously adapt its behavior to enhance the overall effectiveness of its mission. Many such tasks are highly computation intensive. This paper presents the results of a case study that illustrates the effectiveness of an energy-aware, many-core computing architecture to perform on-board path planning within a batteryoperated AUV. A previously published path planning algorithm was ported onto the SCC, an experimental 48 core single-chip system developed by Intel. The performance, power, and energy consumption of the application were measured for different numbers of cores and other system parameters. This case study shows that computation intensive tasks can be executed within an AUV that relies mainly on battery power. Future plans include the deployment and testing of an SCC system within a Teledyne Webb Research Slocum glider.