# An analysis of core- and chip-level architectural features in four generations of Intel server processors

## TL;DR

This paper surveys four generations of Intel server processors, analyzing core and memory hierarchy features and their impact on floating-point workload performance, providing insights for optimizing energy efficiency and benchmark performance.

## Contribution

It offers a detailed comparison of architectural features across four Intel processor generations and evaluates their influence on floating-point workloads and energy efficiency.

## Key findings

- Uncore clock speed tuning improves LINPACK and HPCG energy efficiency.
- Cache snoop mode settings can enhance Graph500 benchmark performance.
- Microbenchmark analysis reveals key factors affecting code performance.

## Abstract

This paper presents a survey of architectural features among four generations of Intel server processors (Sandy Bridge, Ivy Bridge, Haswell, and Broad- well) with a focus on performance with floating point workloads. Starting on the core level and going down the memory hierarchy we cover instruction throughput for floating-point instructions, L1 cache, address generation capabilities, core clock speed and its limitations, L2 and L3 cache bandwidth and latency, the impact of Cluster on Die (CoD) and cache snoop modes, and the Uncore clock speed. Using microbenchmarks we study the influence of these factors on code performance. This insight can then serve as input for analytic performance models. We show that the energy efficiency of the LINPACK and HPCG benchmarks can be improved considerably by tuning the Uncore clock speed without sacrificing performance, and that the Graph500 benchmark performance may profit from a suitable choice of cache snoop mode settings.