Extent of Variation Resilience in Strained CMOS: From Transistors to Digital Circuits
Ahmad Ehteshamul Islam, Charles Augustine, Kaushik Roy, and Muhammad, Ashraful Alam

TL;DR
This paper investigates how uniaxial strain in CMOS transistors enhances variation resilience by affecting mobility and threshold voltage, leading to improved circuit reliability and less severe variability issues.
Contribution
It demonstrates that increasing negative steepness of mobility relationships improves variability resilience, highlighting the importance of mobility-threshold voltage self-compensation in strained CMOS.
Findings
Strain increases negative steepness of mobility relationship.
Variability resilience is enhanced in uniaxial strained CMOS.
Accurate mobility modeling is crucial for reliable SPICE simulations.
Abstract
Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different circuit level optimization schemes to handle these variations. In this paper, we demonstrate how an increase in the negative steepness of the universal mobility relationship improves both the process-related (e.g., oxide thickness fluctuation, gate work-function fluctuation), as well as stress-induced or reliability-related (e.g., Bias Temperature Instability or BTI) parametric variation in CMOS technology. Therefore, we calibrate the universal mobility parameters to reflect the measured variation of negative steepness in uniaxially strained CMOS transistor. This allows us to study the extent of (process-related and stress-induced parametric) variation…
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Taxonomy
TopicsAdvancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis
