# 1-bit Massive MU-MIMO Precoding in VLSI

## TL;DR

This paper introduces novel nonlinear 1-bit precoding algorithms and VLSI architectures for massive MU-MIMO systems with low-resolution DACs, significantly improving error rates and enabling practical high-rate downlink transmission.

## Contribution

It presents the first efficient nonlinear 1-bit precoding algorithms with VLSI designs for massive MU-MIMO, outperforming linear methods in error performance.

## Key findings

- Superior error-rate performance of proposed algorithms
- VLSI architectures enable practical implementation
- FPGA results demonstrate high-rate reliable transmission

## Abstract

Massive multiuser (MU) multiple-input multiple-output (MIMO) will be a core technology in fifth-generation (5G) wireless systems as it offers significant improvements in spectral efficiency compared to existing multi-antenna technologies. The presence of hundreds of antenna elements at the base station (BS), however, results in excessively high hardware costs and power consumption, and requires high interconnect throughput between the baseband-processing unit and the radio unit. Massive MU-MIMO that uses low-resolution analog-to-digital and digital-to-analog converters (DACs) has the potential to address all these issues. In this paper, we focus on downlink precoding for massive MU-MIMO systems with 1-bit DACs at the BS. The objective is to design precoders that simultaneously mitigate multi-user interference (MUI) and quantization artifacts. We propose two nonlinear 1-bit precoding algorithms and corresponding very-large scale integration (VLSI) designs. Our algorithms rely on biconvex relaxation, which enables the design of efficient 1-bit precoding algorithms that achieve superior error-rate performance compared to that of linear precoding algorithms followed by quantization. To showcase the efficacy of our algorithms, we design VLSI architectures that enable efficient 1-bit precoding for massive MU-MIMO systems in which hundreds of antennas serve tens of user equipments. We present corresponding field-programmable gate array (FPGA) implementations to demonstrate that 1-bit precoding enables reliable and high-rate downlink data transmission in practical systems.