Graphene Transport Mediated by Micropatterned Substrates

TL;DR

This paper presents the fabrication and characterization of tunable, topographically patterned substrates for graphene, enabling the study of strain and doping effects on transport properties in graphene devices.

Contribution

It introduces a method to create tunable, topographically patterned substrates suitable for transport measurements in graphene, facilitating new explorations of strain and doping effects.

Findings

Topographic features induce local strain and doping in graphene.

Transport measurements reveal characteristic behavior related to substrate patterning.

Fabrication process allows tunability and compatibility with transport studies.

Abstract

Engineered substrates offer a promising avenue towards graphene devices having tunable properties. In particular, topographically patterned substrates can expose unique behavior due to their ability to induce local variations in strain and electrostatic doping. However, to explore the range of possible science and applications, it is important to create topographic substrates which both have tunable features and are suitable for transport measurements. In this Letter we describe the fabrication of tunable, topographically patterned substrates suitable for transport measurements. We report both optical and transport measurements of graphene devices fabricated on these substrates, and demonstrate characteristic strain and local doping behavior induced by the topographic features.

Equations

$$r=\frac{\Delta {\omega }_{\text{2D}}}{\Delta {\omega }_{\text{G}}}$$

$$r_c=\frac{v_F{m}^{\ast }}{eB}=\frac{\hslash \sqrt{n\pi }}{eB}$$

$$\Delta E_F=e\cdot \alpha \cdot \Delta V_g$$

$$E=\frac{\hslash v_F}{\xi }\text{with}\xi ={\left[\frac{\hslash v_F{x}_0^2}{U}\right]}^{1/3}.$$

$$U=e\cdot V_g\cdot ({\alpha }_{\text{delaminated}}-{\alpha }_{\text{flat}}).$$

Full text

graphene strain transport Raman quantum dot quasibound state

Graphene is a material with enormous potential for both scientific research and technical applications Novoselov et al. (2004, 2005); Zhang et al. (2005); Geim and Novoselov (2007). In particular, the ability to tune graphene’s properties through the use of engineered substrates offers a practical method to explore graphene’s properties and modify them for specific applicationsGuinea, Katsnelson, and Geim (2010); Zhou et al. (2007). Previous work on engineered substrates has employed substrate topographyTomori et al. (2011); Mi et al. (2015); Babichev et al. (2015); Reserbat-Plantey et al. (2014), electrostatic charge injectionChiu et al. (2010), substrate lattice mis-matchZhou et al. (2007), and ferroelectric polarizationHinnefeld et al. (2016) to achieve a range of modifications to graphene’s properties.

Of the various substrate engineering techniques, topographic substrate patterning has two distinct advantages: first, topographic substrates can create local strain in graphene. Strain has large effects on graphene’s electrical properties Pereira and Castro Neto (2009), from inducing minigaps Ni et al. (2008) to creating large pseudo-magnetic fields Guinea, Katsnelson, and Geim (2010); Levy et al. (2010). To date however the techniques used to produce strain in graphene are either not amenable to performing electrical transport measurements on graphene Levy et al. (2010); Tomori et al. (2011); Mohiuddin et al. (2009); Ni et al. (2008); Gill et al. (2015); Reserbat-Plantey et al. (2014) or not compatible with standard lithographic fabrication procedures Babichev et al. (2015). Second, topographic substrates can modulate the effect of a single electrostatic gate to produce complex doping profiles in graphene without the need for multiple, distinct gate electrodes. Here we demonstrate a fabrication procedure for producing engineered arrays of topographic features on standard silicon substrates, and we report optical measurements of strain and transport measurements of local doping in graphene devices fabricated atop these substrates.

The process used to create the topographic features on the substrate is illustrated schematically in Figures 1A-D. First an array of 20 nm thick copper circles is deposited, using standard electron-beam lithography and evaporation techniques, on a silicon chip covered with a 1000 nm layer of thermal oxide. The deposited copper is then used as a mask in a CF4 reactive ion etching (RIE) step to produce cylindrical pillars in the SiO2 layer. The RIE etch time and the diameter of the deposited copper mask circles together define the aspect ratio of the resulting pillars. For these devices we use a mask diameter of 100 nm, and a 10 minute etch time, which gives a height of approximately 200 nm. Pillar diameter is independent of RIE etch time and is equal to the mask diameter. After the etch, the copper mask is removed by immersing the chip in a 0.1M solution of ammonium persulfate for several hours. Finally, the chip is dipped in buffered oxide etchant to sharpen the SiO2 pillars produced during the RIE step into pointed, conical shapes having tips of $\scriptstyle\sim$20 nm diameter.

Graphene devices are fabricated on substrates prepared by this method using the process shown in Figures 1E-F. First Ti/Au (5 nm/30 nm) leads and contact pads are defined and deposited using electron-beam lithography and evaporation. Next, a monolayer of graphene is grown on a different substrate using established chemical vapor deposition techniquesLi et al. (2009a). The graphene is then transferred to the topographic substrate using standard polymer-assisted wet-transfer techniquesLi et al. (2009b). The same polymer layer used to transfer the graphene is then used as a resist in an electron-beam lithography step. Next the exposed graphene is removed using a reactive ion etch, yielding graphene in a Hall bar configuration. Finally the remaining polymer resist is dissolved in acetone and the chip is dried in a critical point drying apparatus. Figure 2 shows scanning electron microscope (SEM) micrographs of substrates and graphene devices produced by this process. Although the transfer and drying process does lead to some ripping of the graphene (see holes evident in Figure 2C) holes and rips cover less than 10% of the surface, leaving the graphene largely robust for transport measurements on the 10 - 50 micron length scale of typical devices. As shown in Figure 2A, we do not observe significant ripple formation Babichev et al. (2015); Reserbat-Plantey et al. (2014), likely because our topographic features are widely spaced Yamamoto et al. (2012).

We perform optical measurements of graphene devices fabricated on these substrates to confirm the presence of strain. Raman spectroscopy iss performed using a Nanophoton Raman 11 microscope with a 532 nm laser at room temperature. The laser power iss kept below 1 mW to minimize local heating. Raman measurements are collected in a raster pattern across a 20 $\mu$m $\times$ 20 $\mu$m area with a measurement spot size of 350 nm; each scan encompasses a varying number of topographic features depending on the array spacing. Random variations in spectra for regions away from topographic features yield shifts of less than $\pm$0.5 cm*-1*. The data for the flat substrates is collected separately for each device to account for the varying residual doping present in each sample. At each raster point the Raman G and 2D peak positions are extractedFerrari et al. (2006). Figures 3A and 3B summarize the extracted positions of the Raman G and 2D peaks, respectively, for graphene on topographically patterned and flat regions of devices prepared by the method described above. Data is shown for devices having pillar spacings between 300 and 700 nm.

Both the G and 2D peaks of graphene on the patterned substrate regions display shifted peak positions relative to graphene on the flat regions. This shift increases with increasing topographic feature spacing and displays a qualitative jump for spacings above 600 nm. We attribute this jump to a snap-through transitionGill et al. (2015); Scharfenberg et al. (2012) in the adhesion of the graphene to the substrate: for spacings below 600 nm the graphene is suspended in the entire topographically patterned region, while for spacings above 600 nm the graphene adheres to the substrate except in the immediate vicinity of a topographic feature. The partial delamination present in the sparse topographic samples produces strain in the graphene which generates the shifted Raman peak positions Gill et al. (2015).

Doping from charge impurities in the substrate is also known to shift Raman peak positions in grapheneReina et al. (2008); Casiraghi et al. (2007), however the ratio

[TABLE]

(where $\Delta\,\omega$ is the shift in a Raman peak position relative to its intrinsic value) differs between the two mechanisms Lee et al. (2012). Experimental measurements Zabel et al. (2012); Metzger et al. (2009); Ding et al. (2010) and theoretical resultsMohr, Maultzsch, and Thomsen (2010); Mohiuddin et al. (2009) place the ratio for strain between 2.25 and 2.8 and the ratio for doping at approximately 0.75 Lee et al. (2012). Figure 3C shows the extracted Raman G and 2D peak positions for a representative topographically patterned sample having a spacing of 700 nm, along with lines corresponding to $r_{\text{strain}}$ (dashed) and $r_{\text{doping}}$ (dotted). The difference between the topographic and flat graphene samples lies along $r_{\text{strain}}$; thus, we attribute the shifted peak positions to the effect of strain in the graphene.

Next we perform magneto-transport measurements on a device having a substrate pillar spacing of 750 nm, to elucidate the effect of local variations in the electrostatic potential. Several similar devices were measured and yielded qualitatively similar results. For sparsely patterned substrates the graphene is locally delaminated in the vicinity of each individual topographic feature. This delamination alters the effective gate capacitance by including a region of vacuum in series with the SiO2 dielectric layer. The local variation in the gate capacitance creates a corresponding variation in the potential, effectively creating a circular potential barrier, e.g. a quantum dot. This situation is illustrated schematically in Figure 4D. Carriers in graphene cannot be confined electrostatically: as massless particles governed by the Dirac equation (in the low energy limit) they display Klein tunneling Katsnelson, Novoselov, and Geim (2006); Young and Kim (2009). However, previous work has shown that circular potential barriers can create pseudo-bound states in graphene Silvestrov and Efetov (2007); Matulis and Peeters (2008); Hewageegana and Apalkov (2008); Chen, Apalkov, and Chakraborty (2007); Heinisch, Bronold, and Fehske (2013). For graphene on topographically patterned substrates we therefore expect transport behavior to display signatures of scattering from these pseudo-bound states. We note that we do not expect coherent transport behavior (such as Fabry-Pérot resonance or superlattice effects) across multiple topographic features, as the coherence length is $\scriptstyle\sim$1 micron Berger et al. (2006)), and a typical device length is 20 $\mu$m which encompasses $\scriptstyle\sim$30 pillars.

Figures 4A and 4B show the results of magneto-transport measurements performed at 250 mK on a 750 nm-spaced topographic device and a flat control device, respectively. Both devices are 20 $\mu$m long and 10 $\mu$m wide; for the topographic device the patterned substrate features cover the entire device area. The Dirac point for both devices is located at approximately 40 V; this reflects both the residual doping from the fabrication process as well as the reduced gate capacitance of the thicker-than-normal SiO2 dielectric layer. All transport measurements were taken with a channel current of 50 nA, and gate leakage current was always less than five percent of channel current. The reduced mobility of the topographic device relative to the flat control device is due to rips introduced during the critical point drying step of the fabrication process. Qualitative differences between the topographic and flat devices are apparent: the flat control device displays the onset of a typical Landau level fan patternBolotin et al. (2009), however the topographic device displays several resistance maxima not present in the control device. Figure 4C shows the same data as Figure 4A with a linear background $R_{\text{background}}=mV_{g}+b$ subtracted; we remove this background to emphasize deviations from the expected Dirac cone pattern of gated graphene. Several additional local maxima are visible in the low gate voltage region. The diamond-like high resistance features (red regions in Figure 4C) are reproducible. Although they are somewhat irregular, they have typical energy scales of $\scriptstyle\sim$1 T in magnetic field, and $\scriptstyle\sim$5 V in gate voltage.

The scale of the observed transport features, in both magnetic field and gate voltage, is in good agreement with theoretical predictions for scattering from quasi-bound states in graphene. Considering first the magnetic field scale, previous workHeinisch, Bronold, and Fehske (2013) has shown that the scattering properties of quantum dots in graphene depend on the size of the dot: for small dots forward scattering is strongly suppressed and conductivity is reduced, while large dots can focus carriers and enhance conductivity. In the presence of a magnetic field, we take the cyclotron radius $r_{c}$ to be the relevant length scale, e.g. for dot size $r<r_{c}$ we expect an effective “small” dot with reduced conductance, while for $r>r_{c}$ we expect a “large” dot with larger conductance. This is consistent with our observation of more resistive behaviour at smaller magnetic fields, i.e. at larger $r_{c}$. This can be estimated quantitatively by calculating the cyclotron radius, given by

[TABLE]

where $v_{F}=10^{6}$ m s*-1* is the Fermi velocity in graphene, $m^{*}$ is the carrier effective mass, $e$ is the charge of an electron, $B$ is the applied magnetic field, $\hbar$ is the reduced Planck’s constant, and $n$ is the carrier density. For our devices, with a field of 1 T corresponding to the the field at which the transport features disappear and a carrier density of $10^{11}$ cm*-2* as determined by separate Hall measurements, we find a cyclotron radius of 40 nm. This is in excellent agreement with the 50 nm radius of the local delamination regions, as determined by SEM measurements.

Next we consider the gate voltage scale of the transport features. Forward scattering off quasi-bound states in graphene quantum dots is also suppressed when the energy of incident carriers matches the energy of a quasi-bound stateSilvestrov and Efetov (2007). We therefore expect the gate voltage scale of the transport features to match the spacing between quasi-bound state energy levels. Features in the transport data are spaced approximately 5V apart. The change in the Fermi energy in graphene for a given change in gate voltage is given by

[TABLE]

where $\alpha=C_{bg}/C_{Q}$ is the capacitive lever arm of the back-gate, the capacitance of the backgate $C_{bg}$ is that of a SiO2 parallel plate capacitor with an area of 200 $\mu$m2 and a separation of 500 nm, and the quantum capacitance of the graphene sheet is given by $C_{Q}=e^{2}\cdot\rho(E_{F})$ Fang et al. (2007) (in the low temperature limit where $E_{F}\gg kT$). The density of states $\rho(E)$ is known for grapheneCastro Neto et al. (2009), and $E_{F}$ can be extracted from the carrier density. Using a carrier density of $10^{11}$ cm*-2* as above this gives an energy scale for the observed transport features of approximately 40 meV. Next we relate this experimental value to theoretical predictions.

For a parabolic potential of the form $V=−(x/x_{0})^{2}U/2$ theoretical results Silvestrov and Efetov (2007) give the following expression for the energy scale of the quasi-bound states:

[TABLE]

As shown in Figure 4D, the potential profile in our devices is defined by the local delamination of graphene in the vicinity of the topographic features. Approximating the potential profile in our devices as parabolic we take $x_{0}=25$ nm to be half the radius of the topographic features, and $U$ to be the change in potential created by the locally varying gate capacitance:

[TABLE]

The capacitive lever arm for the flat region $\alpha_{\text{flat}}$ remains the same as above, and we model the capacitance of the delaminated region as cylinder of air in series with the SiO2 substrate. The cylinder of air has radius $x_{0}$ and height 100 nm, where the latter figure is half the height of the patterned features on the substrate. Taking $V_{g}=22.5\text{V}$ as the midpoint of the region of interest we find a theoretically predicted energy scale of 57 meV for the quasi-bound states in our device, in good agreement with our experimental results.

We note that the energy scale of the quasi-bound states depends on the height of the potential barrier as $E\propto U^{1/3}$. In our experimental configuration the height of the potential barrier depends in turn on the magnitude of the applied gate voltage as $U\propto V_{g}$. The gate voltage in our measurements varies by a factor of two in the region of interest, and so we expect the theoretically predicted energy scale to vary by a factor of $2^{1/3}$ over the course of the measurement, which precludes a more precise quantitative comparison. It is also possible that local strain and pseudomagnetic fields affect transport in this regime. However, our data is consistent with dots having diameters commensurate with the delamination region, rather than localized around the pillars, which implies that delamination may dominate the physics we observe.

In summary, we describe a fabrication procedure for producing graphene devices on substrates having an array of topographic features and we report experimental signatures caused by these features. We find that the spacing of the topographic features determines the adhesion behavior of the graphene; for large spacings partial delamination creates strain in the graphene which we observe using optical measurements. Finally, we find that magneto-transport measurements display features consistent with the presence of a locally varying potential, which we attribute to the variable gate capacitance induced by the local graphene delamination. These transport features are consistent with the presence of quasi-bound states in the graphene; the tunable nature of the graphene delamination offers an opportunity to deliberately engineer the properties of these quasi-bound states. With careful considerations of the topographic feature spacing and height this technique can be adapted to length scales on the order of the coherence length in graphene, thereby offering a novel method to explore correlated strain and electrostatic potentials along with superlattice effects in graphene.