# Sense Amplifier Comparator with Offset Correction for Decision Feedback Equalization based Receivers

## TL;DR

This paper introduces a sense amplifier comparator with integrated offset correction for decision feedback equalization in high-speed receivers, achieving low latency and efficient offset compensation in 130 nm CMOS technology.

## Contribution

It presents a novel offset correction method integrated within the sense amplifier comparator, reducing complexity and latency in decision feedback equalization circuits.

## Key findings

- Operates at 1 GHz frequency
- Consumes 145 μA from 1.2V supply
- Effective offset compensation in CMOS technology

## Abstract

A decision feedback circuit with integrated offset compensation is presented in this paper. The circuit is built around the sense amplifier comparator. The feedback loop is closed around the first stage of the comparator resulting in minimum loop latency. The feedback loop is implemented using a switched capacitor network that picks from one of pre-computed voltages to be fed back. The comparator's offset that is to be compensated for, is added in the same path. Hence, an extra offset correction input is not required. The circuit is used as a receiver for a 10 mm low swing interconnect implemented in UMC 130 nm CMOS technology. The circuit is tested at a frequency of 1 GHz and it consumes 145 $\mu$A from a 1.2V supply at this frequency.