A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code
Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph M\"uller,, Andreas Burg, Claude Thibeault, and Warren J. Gross

TL;DR
This paper presents a high-speed, hardware-implemented list decoder for polar codes that achieves multi-Gbps throughput and competitive error correction, using unrolled architecture adapted for SCL decoding.
Contribution
It introduces an unrolled hardware design for SCL polar decoding, enabling multi-Gbps throughput with high energy efficiency, which was not previously achieved.
Findings
Achieves over 10 Gbps throughput at 468 MHz
Energy efficiency of 7.25 pJ/bit in 28 nm CMOS
Competitive error correction performance with LDPC codes
Abstract
Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more complex successive-cancellation list (SCL) decoding algorithm is gathering more attention lately as it significantly improves the error-correction performance of short- to moderate-length polar codes, especially when they are concatenated with a cyclic redundancy check code. However, as SCL decoding explores several decoding paths, existing hardware implementations tend to be significantly slower than SC-based decoders. In this paper, we show how the unrolling technique, which has already been used in the context of SC decoding, can be adapted to SCL decoding yielding a multi-Gbps SCL-based polar decoder with an error-correction performance that is…
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