FPGA Architecture for Deep Learning and its application to Planetary Robotics

TL;DR

This paper develops a FPGA-based hardware accelerator for Q-learning with neural networks, enabling faster and more efficient autonomous learning for planetary rovers within space hardware constraints.

Contribution

It introduces a novel FPGA architecture for Q-learning with neural networks, demonstrating significant speedup and efficiency improvements over traditional CPUs for space applications.

Findings

Up to 43-fold speedup on Virtex 7 FPGA compared to Intel i5 CPU.

Effective implementation of single neuron and multilayer perceptron Q-learning.

Simulated architecture shows promising performance and power efficiency.

Abstract

Autonomous control systems onboard planetary rovers and spacecraft benefit from having cognitive capabilities like learning so that they can adapt to unexpected situations in-situ. Q-learning is a form of reinforcement learning and it has been efficient in solving certain class of learning problems. However, embedded systems onboard planetary rovers and spacecraft rarely implement learning algorithms due to the constraints faced in the field, like processing power, chip size, convergence rate and costs due to the need for radiation hardening. These challenges present a compelling need for a portable, low-power, area efficient hardware accelerator to make learning algorithms practical onboard space hardware. This paper presents a FPGA implementation of Q-learning with Artificial Neural Networks (ANN). This method matches the massive parallelism inherent in neural network software with the fine-grain parallelism of an FPGA hardware thereby dramatically reducing processing time. Mars Science Laboratory currently uses Xilinx-Space-grade Virtex FPGA devices for image processing, pyrotechnic operation control and obstacle avoidance. We simulate and program our architecture on a Xilinx Virtex 7 FPGA. The architectural implementation for a single neuron Q-learning and a more complex Multilayer Perception (MLP) Q-learning accelerator has been demonstrated. The results show up to a 43-fold speed up by Virtex 7 FPGAs compared to a conventional Intel i5 2.3 GHz CPU. Finally, we simulate the proposed architecture using the Symphony simulator and compiler from Xilinx, and evaluate the performance and power consumption.