Coding for Racetrack Memories
Yeow Meng Chee, Han Mao Kiah, Alexander Vardy, Van Khu Vu, and Eitan, Yaakobi

TL;DR
This paper introduces coding schemes to correct shift errors in racetrack memory, leveraging multiple read heads to achieve reliable data retrieval with minimal redundancy, addressing both deletion and insertion errors.
Contribution
It proposes novel codes that utilize multiple heads in racetrack memory to correct shift errors efficiently with minimal redundancy.
Findings
Can correct up to d deletions with d+1 heads
Effective correction of burst deletions and sticky insertions
Achieves reliable data recovery with at most one redundant bit
Abstract
Racetrack memory is a new technology which utilizes magnetic domains along a nanoscopic wire in order to obtain extremely high storage density. In racetrack memory, each magnetic domain can store a single bit of information, which can be sensed by a reading port (head). The memory has a tape-like structure which supports a shift operation that moves the domains to be read sequentially by the head. In order to increase the memory's speed, prior work studied how to minimize the latency of the shift operation, while the no less important reliability of this operation has received only a little attention. In this work we design codes which combat shift errors in racetrack memory, called position errors. Namely, shifting the domains is not an error-free operation and the domains may be over-shifted or are not shifted, which can be modeled as deletions and sticky insertions. While it is…
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Taxonomy
TopicsDNA and Biological Computing · Advanced biosensing and bioanalysis techniques · Advanced Data Storage Technologies
