MorphoNoC: Exploring the Design Space of a Configurable Hybrid NoC using Nanophotonics

TL;DR

MorphoNoC is a scalable, configurable hybrid network-on-chip architecture that integrates nanophotonic links to improve latency and energy efficiency in multi-core systems.

Contribution

This paper introduces MorphoNoC, a novel hybrid NoC design combining electrical and nanophotonic links, with detailed analysis of photonic link design and network-level optimization.

Findings

Up to 3.0x latency reduction

Up to 1.37x energy savings

Effective trade-offs between energy and latency

Abstract

As diminishing feature sizes drive down the energy for computations, the power budget for on-chip communication is steadily rising. Furthermore, the increasing number of cores is placing a huge performance burden on the network-on-chip (NoC) infrastructure. While NoCs are designed as regular architectures that allow scaling to hundreds of cores, the lack of a flexible topology gives rise to higher latencies, lower throughput, and increased energy costs. In this paper, we explore MorphoNoCs - scalable, configurable, hybrid NoCs obtained by extending regular electrical networks with configurable nanophotonic links. In order to design MorphoNoCs, we first carry out a detailed study of the design space for Multi-Write Multi-Read (MWMR) nanophotonics links. After identifying optimum design points, we then discuss the router architecture for deploying them in hybrid electronic-photonic NoCs. We then study explore the design space at the network level, by varying the waveguide lengths and the number of hybrid routers. This affords us to carry out energy-latency trade-offs. For our evaluations, we adopt traces from synthetic benchmarks as well as the NAS Parallel Benchmark suite. Our results indicate that MorphoNoCs can achieve latency improvements of up to 3.0x or energy improvements of up to 1.37x over the base electronic network.

Full text

See pages 1-last of morphonoc-exploring-design.pdf