# Subnanosecond Time-to-Digital Converter Implemented in a Kintex-7 FPGA

## TL;DR

This paper presents an eight-channel, subnanosecond resolution TDC implemented in a Kintex-7 FPGA, offering a simple, robust, and temperature-stable solution suitable for high-energy physics applications.

## Contribution

The paper introduces a novel multisampling scheme-based TDC with variable bin size in FPGA, achieving subnanosecond resolution without calibration.

## Key findings

- Bin size down to 0.28 ns with low differential nonlinearity
- Stable performance across temperature variations
- Low power consumption and scalable channel count

## Abstract

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.