Performance of Step Network Using Simulation Tool

TL;DR

This paper evaluates the performance of different queuing disciplines in a distributed network simulation using a step topology, focusing on metrics like delay, packet loss, and resource utilization.

Contribution

It introduces a simulation-based analysis of queuing mechanisms in heterogeneous networks with step topology, comparing their impact on QoS for various traffic types.

Findings

Priority queuing reduces packet delay for high-priority traffic.

Weighted fair queuing balances resource utilization across traffic types.

Different queuing disciplines significantly affect network performance metrics.

Abstract

Nowadays distributed computing approach has become very popular due to several advantages over the centralized computing approach as it also offers high performance computing at a very low cost. Each router implements some queuing mechanism for resources allocation in a best possible optimize manner and governs with packet transmission and buffer mechanism. In this paper, different types of queuing disciplines have been implemented for packet transmission when the bandwidth is allocated as well as packet dropping occurs due to buffer overflow. This gives result in latency in packet transmission, as the packet has to wait in a queue which is to be transmitted again. Some common queuing mechanisms are first in first out, priority queue and weighted fair queuing, etc. This targets simulation in heterogeneous environment through simulator tool to improve the quality of services by evaluating the performance of said queuing disciplines. This is demonstrated by interconnecting heterogeneous devices through step topology. In this paper, authors compared data packet, voice and video traffic by analyzing the performance based on packet dropped rate, delay variation, end to end delay and queuing delay and how the different queuing discipline effects the applications and utilization of network resources at the routers. Before evaluating the performance of the connected devices, a Unified Modeling Language class diagram is designed to represent the static model for evaluating the performance of step topology. Results are described by taking the various case studies.