Complete DFM Model for High-Performance Computing SoCs with Guard Ring and Dummy Fill Effect

TL;DR

This paper investigates the impact of layout effects, including guard rings and dummy fills, on high-performance computing SoC performance using a comprehensive DFM model in 28nm technology.

Contribution

It introduces a complete DFM model that incorporates guard ring and dummy fill effects, which are previously under-studied in layout impact analysis.

Findings

Guard ring and dummy fill effects significantly influence circuit performance.

The proposed model accurately predicts layout effects in 28nm technology.

Experimental validation confirms the importance of considering these effects in design.

Abstract

For nanotechnology, the semiconductor device is scaled down dramatically with additional strain engineering for device enhancement, the overall device characteristic is no longer dominated by the device size but also circuit layout. The higher order layout effects, such as well proximity effect (WPE), oxide spacing effect (OSE) and poly spacing effect (PSE), play an important role for the device performance, it is critical to understand Design for Manufacturability (DFM) impacts with various layout topology toward the overall circuit performance. Currently, the layout effects (WPE, OSE and PSE) are validated through digital standard cell and analog differential pair test structure. However, two analog layout structures: the guard ring and dummy fill impact are not well studied yet, then, this paper describes the current mirror test circuit to examine the guard ring and dummy fills DFM impacts using TSMC 28nm HPM process.