Memory Efficient Multi-Scale Line Detector Architecture for Retinal Blood Vessel Segmentation

TL;DR

This paper introduces a memory-efficient, FPGA-based architecture for real-time retinal blood vessel detection using the Multi-Scale Line Detector algorithm, significantly reducing memory use and increasing processing speed.

Contribution

The paper presents a novel FPGA implementation of MSLD that drastically reduces memory requirements and enhances processing speed for retinal blood vessel segmentation.

Findings

Achieves 70x speedup on low-resolution images

Achieves 323x speedup on high-resolution images

Maintains comparable accuracy to software version

Abstract

This paper presents a memory efficient architecture that implements the Multi-Scale Line Detector (MSLD) algorithm for real-time retinal blood vessel detection in fundus images on a Zynq FPGA. This implementation benefits from the FPGA parallelism to drastically reduce the memory requirements of the MSLD from two images to a few values. The architecture is optimized in terms of resource utilization by reusing the computations and optimizing the bit-width. The throughput is increased by designing fully pipelined functional units. The architecture is capable of achieving a comparable accuracy to its software implementation but 70x faster for low resolution images. For high resolution images, it achieves an acceleration by a factor of 323x.