Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits

TL;DR

This study quantifies the likelihood of multiple bit-flips caused by particle strikes in logic circuits, revealing that gate strikes can cause up to 50% multiple errors, highlighting the need for hardened designs.

Contribution

It provides a detailed characterization of multiple bit-flip probabilities due to single event transients using post-layout simulations and Monte Carlo sampling.

Findings

Substantial fraction of SEU outcomes involve multiple register flips.

Probability of multiple flips from gate strikes can reach up to 50%.

Register strikes cause about 2% multiple flips, but gate strikes are more likely to cause multiple errors.

Abstract

High energy particles from cosmic rays or packaging materials can generate a glitch or a current transient (single event transient or SET) in a logic circuit. This SET can eventually get captured in a register resulting in a flip of the register content, which is known as soft error or single-event upset (SEU). A soft error is typically modeled as a probabilistic single bit-flip model. In developing such abstract fault models, an important issue to consider is the likelihood of multiple bit errors caused by particle strikes. The fact that an SET causes multiple flips is noted in the literature. We perform a characterization study of the impact of an SET on a logic circuit to quantify the extent to which an SET can cause multiple bit flips. We use post-layout circuit simulations and Monte Carlo sampling scheme to get accurate bit-flip statistics. We perform our simulations on ISCAS'85, ISCAS'89 and ITC'99 benchmarks in 180nm and 65nm technologies. We find that a substantial fraction of SEU outcomes had multiple register flips. We futher analyse the individual contributions of the strike on a register and the strike on a logic gate, to multiple flips. We find that, amongst the erroneous outcomes, the probability of multiple bit-flips for 'gate-strike' cases was substantial and went up to 50%, where as those for 'register-strike' cases was just about 2%. This implies that, in principle, we can eliminate the flips due to register strikes using hardened flip-flop designs. However, in such designs, out of the remaining flips which will be due to gate strikes, a large fraction is likely to be multiple flips.