Application-aware Retiming of Accelerators: A High-level Data-driven Approach

TL;DR

This paper introduces a data-driven high-level approach for retiming accelerators in adaptive systems, focusing on memory distribution to optimize area, performance, and power in elastic circuits.

Contribution

It presents a novel memory-aware retiming technique for elastic circuits, enhancing high-level synthesis by considering memory distribution and slack elasticity.

Findings

Improved area and power efficiency in synthesized elastic circuits.

Enhanced performance through optimized memory distribution.

Effective retiming strategies for adaptive FPGA-based accelerators.

Abstract

Flexibility at hardware level is the main driving force behind adaptive systems whose aim is to realise microarhitecture deconfiguration 'online'. This feature allows the software/hardware stack to tolerate drastic changes of the workload in data centres. With emerge of FPGA reconfigurablity this technology is becoming a mainstream computing paradigm. Adaptivity is usually accompanied by the high-level tools to facilitate multi-dimensional space exploration. An essential aspect in this space is memory orchestration where on-chip and off-chip memory distribution significantly influences the architecture in coping with the critical spatial and timing constraints, e.g. Place and Route. This paper proposes a memory smart technique for a particular class of adaptive systems: Elastic Circuits which enjoy slack elasticity at fine level of granularity. We explore retiming of a set of popular benchmarks via investigating the memory distribution within and among accelerators. The area, performance and power patterns are adopted by our high-level synthesis framework, with respect to the behaviour of the input descriptions, to improve the quality of the synthesised elastic circuits.