Node Aware Sparse Matrix-Vector Multiplication

TL;DR

This paper introduces a node-aware parallel sparse matrix-vector multiplication method that leverages system topology knowledge to reduce communication costs and improve scalability in parallel computations.

Contribution

The paper presents a novel node-aware approach for SpMV that minimizes communication by redistributing input vector values based on node-processor layout.

Findings

Significant reduction in communication costs observed.

Improved parallel scalability demonstrated.

Efficiency gains across various computational experiments.

Abstract

The sparse matrix-vector multiply (SpMV) operation is a key computational kernel in many simulations and linear solvers. The large communication requirements associated with a reference implementation of a parallel SpMV result in poor parallel scalability. The cost of communication depends on the physical locations of the send and receive processes: messages injected into the network are more costly than messages sent between processes on the same node. In this paper, a node aware parallel SpMV (NAPSpMV) is introduced to exploit knowledge of the system topology, specifically the node-processor layout, to reduce costs associated with communication. The values of the input vector are redistributed to minimize both the number and the size of messages that are injected into the network during a SpMV, leading to a reduction in communication costs. A variety of computational experiments that highlight the efficiency of this approach are presented.