On Fault-Tolerant Design of Exclusive-OR Gates in QCA
Dharmendra Kumar, Debasis Mitra, Bhargab B. Bhattacharya

TL;DR
This paper addresses the lack of fault-tolerance in QCA XOR gates by proposing new designs that are resilient to manufacturing defects, with improved area and delay metrics, facilitating practical and low-cost fabrication.
Contribution
It introduces realistic, fault-tolerant QCA XOR gate designs that outperform existing schemes in area, delay, and defect resilience, enabling practical QCA circuit implementation.
Findings
Existing fault-tolerant schemes are impractical due to high area and delay.
Proposed designs show high fault-tolerance against various cell misplacement defects.
The designs enable low-cost fabrication due to the absence of crossing.
Abstract
Design paradigms of logic circuits with Quantum-dot Cellular Automata (QCA) have been extensively studied in the recent past. Unfortunately, due to the lack of mature fabrication support, QCA-based circuits often suffer from various types of manufacturing defects and variations, and therefore, are unreliable and error-prone. QCA-based Exclusive-OR (XOR) gates are frequently used in the construction of several computing subsystems such as adders, linear feedback shift registers, parity generators and checkers. However, none of the existing designs for QCA XOR gates have considered the issue of ensuring fault-tolerance. Simulation results also show that these designs can hardly tolerate any fault. We investigate the applicability of various existing fault-tolerant schemes such as triple modular redundancy (TMR), NAND multiplexing, and majority multiplexing in the context of practical…
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Taxonomy
TopicsQuantum-Dot Cellular Automata · Advanced Memory and Neural Computing · Semiconductor materials and devices
