Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing

TL;DR

This paper introduces a passive switched-capacitor matrix multiplier designed for approximate computing and machine learning, demonstrating high energy efficiency and practical applications in neural networks and optimization problems.

Contribution

It presents a novel passive switched-capacitor multiplier with integrated ADC, analyzing charge accumulation and noise, and showcases its effectiveness in neural network feature extraction and analog optimization.

Findings

Achieves 8.7 TOPS/W at 1 GHz for neural network applications.

Attains 7.7 TOPS/W at 2.5 GHz for optimization acceleration.

Demonstrates practical implementation with 40 nm CMOS fabrication.

Abstract

A switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications. The multiply-and-accumulate operations perform discrete-time charge-domain signal processing using passive switches and 300 aF unit capacitors. The computation is digitized with a 6 b asynchronous successive approximation register analog-to-digital converter. The analyses of incomplete charge accumulation and thermal noise are discussed. The design was fabricated in 40 nm CMOS, and experimental measurements of multiplication are illustrated using matched filtering and image convolutions to analyze noise and offset. Two applications are highlighted: 1) energy-efficient feature extraction layer performing both compression and classification in a neural network for an analog front end and 2) analog acceleration for solving optimization problems that are traditionally performed in the digital domain. The chip obtains measured efficiencies of 8.7 TOPS/W at 1 GHz for the first application and 7.7 TOPS/W at 2.5 GHz for the second application.