An Efficient Partial Sums Generator for Constituent Code based Successive Cancellation Decoding of Polar Codes

TL;DR

This paper introduces a specialized, efficient partial sum generator architecture for constituent code-based polar code decoders, significantly improving timing and reducing overhead in hardware implementations.

Contribution

It presents the first purposefully designed partial sum generator tailored for constituent code-based polar decoders, enhancing decoding speed and efficiency.

Findings

Achieved low-latency decoding with the new generator

Reduced hardware overhead compared to conventional designs

Validated performance through ASIC and FPGA implementations

Abstract

This paper proposes the architecture of partial sum generator for constituent codes based polar code decoder. Constituent codes based polar code decoder has the advantage of low latency. However, no purposefully designed partial sum generator design exists that can yield desired timing for the decoder. We first derive the mathematical presentation with the partial sums set $\bm{\beta^c}$ which is corresponding to each constituent codes. From this, we concoct a shift-register based partial sum generator. Next, the overall architecture and design details are described, and the overhead compared with conventional partial sum generator is evaluated. Finally, the implementation results with both ASIC and FPGA technology and relevant discussions are presented.