Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires
Ilias Giechaskiel, Kasper B. Rasmussen, Ken Eguro

TL;DR
This paper uncovers a side-channel in FPGAs where long wires leak information through propagation delay variations, enabling covert communication and data exfiltration, with high accuracy and potential for countermeasures.
Contribution
It demonstrates a novel information leakage channel via FPGA routing wires, quantifies its effectiveness, and discusses mitigation strategies.
Findings
Leakage detectable with small circuits
Achieves over 99% accuracy in inference
Supports data rates up to 6kbps
Abstract
Field-Programmable Gate Arrays (FPGAs) are integrated circuits that implement reconfigurable hardware. They are used in modern systems, creating specialized, highly-optimized integrated circuits without the need to design and manufacture dedicated chips. As the capacity of FPGAs grows, it is increasingly common for designers to incorporate implementations of algorithms and protocols from a range of third-party sources. The monolithic nature of FPGAs means that all on-chip circuits, including third party black-box designs, must share common on-chip infrastructure, such as routing resources. In this paper, we observe that a "long" routing wire carrying a logical 1 reduces the propagation delay of other adjacent but unconnected long wires in the FPGA interconnect, thereby leaking information about its state. We exploit this effect and propose a communication channel that can be used for…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
