Computing with volatile memristors: An application of non-pinched hysteresis

TL;DR

This paper demonstrates in-memory computing using volatile memristors with non-pinched hysteresis, showcasing a graphene-based prototype and modeling its behavior for logic gate implementation.

Contribution

It introduces a memristive model for volatile graphene-based devices and identifies parameter regions for in-memory logic operations.

Findings

Successful simulation of in-memory logic gates

Identification of parameter regions for logic functions

Prototype of volatile memristor with non-pinched hysteresis

Abstract

The possibility of in-memory computing with volatile memristive devices, namely, memristors requiring a power source to sustain their memory, is demonstrated. We have adopted a hysteretic graphene-based field emission structure as a prototype of volatile memristor, which is characterized by a non-pinched hysteresis loop. Memristive model of the structure is developed and used to simulate a polymorphic circuit implementing in-memory computing gates such as the material implication. Specific regions of parameter space realizing useful logic functions are identified. Our results are applicable to other realizations of volatile memory devices.