Fast and reconfigurable packet classification engine in FPGA-based firewall
Arief Wicaksana (ITB), Arif Sasongko (ITB)

TL;DR
This paper introduces a fast, reconfigurable FPGA-based Packet Classification Engine (PCE) for firewalls that uses a tree-based algorithm to efficiently inspect packet headers, enhancing security and scalability.
Contribution
The paper presents a novel FPGA architecture for packet classification that simplifies multidimensional inspection using a tree-based algorithm, achieving high speed and reconfigurability.
Findings
Achieves 91 MHz clock frequency on Cyclone II FPGA.
Inspects multiple header fields in one clock cycle.
Provides a scalable and adaptable classification system.
Abstract
In data communication via internet, security is becoming one of the most influential aspects. One way to support it is by classifying and filtering ethernet packets within network devices. Packet classification is a fundamental task for network devices such as routers, firewalls, and intrusion detection systems. In this paper we present architecture of fast and reconfigurable Packet Classification Engine (PCE). This engine is used in FPGA-based firewall. Our PCE inspects multi-dimensional field of packet header sequentially based on tree-based algorithm. This algorithm simplifies overall system to a lower scale and leads to a more secure system. The PCE works with an adaptation of single cycle processor architecture in the system. Ethernet packet is examined with PCE based on Source IP Address, Destination IP Address, Source Port, Destination Port, and Protocol fields of the packet…
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