FPGA Implementation of a Scalable and Run-Time Adaptable Multi-Standard Packet Detector

TL;DR

This paper presents a modular FPGA-based design for a multi-standard packet detector that is scalable and adaptable at run-time, supporting rapid prototyping for OFDM communication standards.

Contribution

It introduces a flexible, modular FPGA implementation with generic control for quick development of preamble-based packet detectors for various standards.

Findings

Implemented on Xilinx Virtex-6 FPGA with MicroBlaze processor

Supports rapid prototyping and run-time adaptability

Demonstrates scalability for multiple OFDM standards

Abstract

This paper describes a step by step approach for implementing a scalable and run-time adaptable multi-standard packet detector for orthogonal frequency divisional multiplexing (OFDM) based communication standards. The paper briefly describes considerations and design choices in making a modular system block with generic control supporting rapid prototyping and implementation of preamble-based packet detectors. The results were generated through implementation on a Xilinx Virtex-6 FPGA with a MicroBlaze processor instantiated to provide run-time control and adaptability.