Multipliers: comparison of Fourier transformation based method and Synopsys design technique for up to 32 bits inputs in regular and saturation arithmetics

TL;DR

This paper compares a Fourier transformation-based hardware multiplication method with Synopsys design techniques, demonstrating higher efficiency and speed for small to medium bit-range inputs in regular and saturation arithmetic.

Contribution

It introduces a Fourier transformation-based multiplication technique optimized for 2-8 bit inputs and compares its performance to Synopsys methods.

Findings

Up to 20% faster for 2-8 bit inputs

Up to 3% faster for 8-32 bit inputs

Efficient implementation using minimized Boolean functions

Abstract

The technique for hardware multiplication based upon Fourier transformation has been introduced. The technique has the highest efficiency on multiplication units with up to 8 bit range. Each multiplication unit is realized on base of the minimized Boolean functions. Experimental data showed that this technique the multiplication process speed up to 20% higher for 2-8 bit range of input operands and up to 3% higher for 8-32 bit range of input operands than analogues designed by Synopsys technique.