Efficient Parallel Verification of Galois Field Multipliers

TL;DR

This paper introduces a parallel algebraic verification method for Galois field multipliers that significantly improves efficiency by leveraging bit-parallel processing, enabling verification of large multipliers up to 571 bits.

Contribution

It presents a novel algebraic functional verification technique that verifies GF multipliers in parallel, overcoming the sequential limitations of previous methods.

Findings

Verified GF multipliers up to 571 bits.

Achieved high efficiency through parallel processing.

Demonstrated effectiveness on Mastrovito and Montgomery multipliers.

Abstract

Galois field (GF) arithmetic is used to implement critical arithmetic components in communication and security-related hardware, and verification of such components is of prime importance. Current techniques for formally verifying such components are based on computer algebra methods that proved successful in verification of integer arithmetic circuits. However, these methods are sequential in nature and do not offer any parallelism. This paper presents an algebraic functional verification technique of gate-level GF (2m ) multipliers, in which verification is performed in bit-parallel fashion. The method is based on extracting a unique polynomial in Galois field of each output bit independently. We demonstrate that this method is able to verify an n-bit GF multiplier in n threads. Experiments performed on pre- and post-synthesized Mastrovito and Montgomery multipliers show high efficiency up to 571 bits.