Non-ideal memristors for a non-ideal world

TL;DR

This paper extends memristor theory to include various non-idealities, demonstrating how background currents, degradation resistance, and filament modeling affect hysteresis behavior and asymmetry in I-V characteristics.

Contribution

It introduces new models for non-ideal memristors and a novel measurement method for hysteresis asymmetry, linking device behavior to underlying physical mechanisms.

Findings

Background current shifts crossing point from zero

Degradation resistance causes asymmetry in hysteresis

Filament model explains triangular V-I curves

Abstract

Memristors have pinched hysteresis loops in the $V-I$ plane. Ideal memristors are everywhere non-linear, cross at zero and are rotationally symmetric. In this paper we extend memristor theory to produce different types of non-ideality and find that: including a background current (such as an ionic current) moves the crossing point away from zero; including a degradation resistance (that increases with experimental time) leads to an asymmetry; modelling a low resistance filament in parallel describes triangular $V-I$ curves with a straight-line low resistance state. A novel measurement of hysteresis asymmetry was introduced based on hysteresis and it was found that which lobe was bigger depended on the size of the breaking current relative to the memristance. The hysteresis varied differently with each type of non-ideality, suggesting that measurements of several device I-V curves and calculation of these parameters could give an indication of the underlying mechanism.