Studies of irradiated AMS H35 CMOS detectors for the ATLAS tracker upgrade

TL;DR

This study evaluates the radiation hardness of AMS H35 CMOS detectors, specifically the H35Demo ASIC, for potential use in the ATLAS tracker upgrade at the High Luminosity LHC, focusing on depletion region evolution under irradiation.

Contribution

It provides the first detailed analysis of the radiation effects on H35 CMOS detectors, including the evolution of the depletion region with fluence using edge-TCT measurements.

Findings

Depletion region decreases with increased fluence.

Detectors with different substrate resistivities show varied radiation responses.

Devices withstand fluences up to 2 x 10^15 n_eq/cm^2 without catastrophic failure.

Abstract

Silicon detectors based on the HV-CMOS technology are being investigated as possible candidate for the outer layers of the ATLAS pixel detector for the High Luminosity LHC. In this framework the H35Demo ASIC has been produced in the 350 nm AMS technology (H35). The H35Demo chip has a large area ($18.49 \times 24.40 \, \mathrm{mm^2}$) and includes four different pixel matrices and three test structures. In this paper the radiation hardness properties, in particular the evolution of the depletion region with fluence is studied using edge-TCT on test structures. Measurements on the test structures from chips with different substrate resistivity are shown for non irradiated and irradiated devices up to a cumulative fluence of $2 \cdot 10^{15} \, \mathrm{1\,MeV\, n_{eq} / cm^{2}}$.