Temperature-Insensitive Analog Vector-by-Matrix Multiplier Based on 55 nm NOR Flash Memory Cells

TL;DR

This paper presents a high-density, temperature-insensitive analog vector-by-matrix multiplier using 55 nm NOR flash memory cells with high-precision tuning and low temperature drift, suitable for advanced analog computing applications.

Contribution

It introduces a novel design of a dense, temperature-stable analog multiplier based on redesigned NOR flash memory arrays with sub-1% tuning accuracy.

Findings

Achieved 0.33 μm² per cell density, surpassing prior nonvolatile memory implementations.

Demonstrated ~2% precision in vector-by-vector multiplication.

Sub-3% temperature drift of output signal between 25°C and 85°C.

Abstract

We have fabricated and successfully tested an analog vector-by-matrix multiplier, based on redesigned 10x12 arrays of 55 nm commercial NOR flash memory cells. The modified arrays enable high-precision individual analog tuning of each cell, with sub-1% accuracy, while keeping the highly optimized cells, with their long-term state retention, intact. The array has an area of 0.33 um^2 per cell, and is at least one order of magnitude more dense than the reported prior implementations of nonvolatile analog memories. The demonstrated vector-by-vector multiplier, using gate coupling to additional periphery cells, has ~2% precision, limited by the aggregate effect of cell noise, retention, mismatch, process variations, tuning precision, and capacitive crosstalk. A differential version of the multiplier has allowed us to demonstrate sub-3% temperature drift of the output signal in the range between 25C and 85C.