Power Gating Structure for Reversible Programmable Logic Array

TL;DR

This paper introduces a power gating structure for reversible programmable logic arrays to reduce sub-threshold leakage power, achieving significant energy savings and improved transient response compared to traditional CMOS designs.

Contribution

The paper presents a novel power gating approach for reversible logic arrays, specifically using sleep transistors, to reduce power dissipation at the physical design level.

Findings

40.8% energy savings compared to CMOS design

Improved transient response during switching activity

Effective reduction of sub-threshold leakage in reversible logic systems

Abstract

Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array (RPLA) is one of the important parts of the low power industrial applications and in this paper the physical design of the RPLA is presented by using the sleep transistor and the results is shown with the help of TINA- PRO software. The results for the proposed design is also compare with the CMOS design and shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the switching activity and showing that the proposed design is much better that the modern CMOS design of the RPLA.