Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks
Arash Ardakani, Carlo Condo, Warren J. Gross

TL;DR
This paper introduces sparsely-connected neural networks that significantly reduce connections and memory usage, leading to lower energy consumption and maintained or improved accuracy on standard datasets, facilitating more efficient VLSI implementations.
Contribution
It proposes a novel sparsely-connected neural network architecture and an efficient hardware design that drastically reduces memory and energy requirements while maintaining high accuracy.
Findings
Up to 90% reduction in network connections.
Up to 90% memory savings in hardware implementation.
Up to 84% energy reduction per neuron.
Abstract
Recently deep neural networks have received considerable attention due to their ability to extract and represent high-level abstractions in data sets. Deep neural networks such as fully-connected and convolutional neural networks have shown excellent performance on a wide range of recognition and classification tasks. However, their hardware implementations currently suffer from large silicon area and high power consumption due to the their high degree of complexity. The power/energy consumption of neural networks is dominated by memory accesses, the majority of which occur in fully-connected networks. In fact, they contain most of the deep neural network parameters. In this paper, we propose sparsely-connected networks, by showing that the number of connections in fully-connected networks can be reduced by up to 90% while improving the accuracy performance on three popular datasets…
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Taxonomy
TopicsAdvanced Neural Network Applications · Advanced Memory and Neural Computing · Machine Learning and ELM
