Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips

TL;DR

This paper investigates design-induced variation in modern DRAM chips, characterizes its impact on error vulnerability, and proposes low-cost mechanisms to dynamically optimize DRAM latency for improved system performance.

Contribution

It empirically demonstrates design-induced variation in real DRAM chips and introduces two novel mechanisms, DIVA Profiling and DIVA Shuffling, to reduce latency reliably.

Findings

Design-induced variation is consistent across DRAM generations.

DIVA Profiling dynamically finds the lowest reliable DRAM latency.

DIVA Shuffling mitigates errors by mapping vulnerable regions across ECC codewords.

Abstract

Variation has been shown to exist across the cells within a modern DRAM chip. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the design and placement of different components in the DRAM chip. Our goals are to understand design-induced variation that exists in real, state-of-the-art DRAM chips, exploit it to develop low-cost mechanisms that can dynamically find and use the lowest latency at which to operate a DRAM chip reliably, and, thus, improve overall system performance while ensuring reliable system operation. To this end, we first experimentally demonstrate and analyze designed-induced variation in modern DRAM devices by testing and characterizing 96 DIMMs (768 DRAM chips). Our characterization identifies DRAM regions that are vulnerable to errors, if operated at lower latency, and finds consistency in their locations across a given DRAM chip generation, due to design-induced variation. Based on our extensive experimental analysis, we develop two mechanisms that reliably reduce DRAM latency. First, DIVA Profiling uses runtime profiling to dynamically identify the lowest DRAM latency that does not introduce failures. DIVA Profiling exploits design-induced variation and periodically profiles only the vulnerable regions to determine the lowest DRAM latency at low cost. Our second mechanism, DIVA Shuffling, shuffles data such that values stored in vulnerable regions are mapped to multiple error-correcting code (ECC) codewords. Combined together, our two mechanisms reduce read/write latency by 40.0%/60.5%, which translates to an overall system performance improvement of 14.7%/13.7%/13.8% (in 2-/4-/8-core systems) across a variety of workloads, while ensuring reliable operation.