Design of a Compact Reversible Read-Only-Memory with MOS Transistors

TL;DR

This paper introduces a novel reversible ROM design using CMOS transistors, including a new reversible gate, to achieve low power dissipation and optimal efficiency, verified through simulations and theoretical analysis.

Contribution

It presents the first reversible ROM architecture with CMOS implementation and introduces the NP gate, optimizing gate count, transistors, and garbage outputs.

Findings

Design achieves low power dissipation.

Optimized in terms of gates, transistors, and garbage outputs.

Simulation results verify correctness and efficiency.

Abstract

Energy conservative devices are the need of the modern technology which leads to the development of reversible logic. The synthesis of reversible logic has become an intensely studied area as it overcomes the problem of power dissipation associated with irreversibility. Storage device such as Read-Only-Memory (ROM) can be realized in a reversible way with low power dissipation. The reversibility of ROM has not been yet realized in literature and hence, this paper presents a novel reversible ROM with its Complementary Metal Oxide Semiconductor (CMOS) realization. On the way to present the architecture of reversible ROM, we propose a new reversible gate named as Nowrin Papiya (NP) gate. All the proposed circuits and gates are realized with CMOS based pass transistor logic. Finally, an algorithm as well as several theorems on the numbers of gates, transistors and garbage outputs have been presented to show the optimality of the reversible ROM. Simulations using Microwind DSCH software has been shown to verify the correctness of the proposed design. The comparative results prove that the proposed designs are efficient and optimized in terms of numbers of gates, transistors, garbage outputs, quantum cost and delay.