CMOS-Memristor Hybrid Integrated Pixel Sensors

TL;DR

This paper introduces CMOS-memristor hybrid pixel sensors that combine MOSFETs and memristors to enhance image sensor resolution, reduce area, and enable scalable, high-speed pixel parallel processing.

Contribution

It proposes novel 2T-M and 3T-M pixel configurations integrating memristors with CMOS, improving area efficiency and scalability for high-resolution image sensors.

Findings

Reduced pixel area due to memristor integration

Enhanced scalability through layered memristor-MOSFET arrays

Potential for high-speed, high-resolution image processing

Abstract

Increase in image resolution require the ability of image sensors to pack an increased number of circuit components in a given area. On the the other hand a high speed processing of signals from the sensors require the ability of pixel to carry out pixel parallel operations. In the paper, we propose a modified 3T and 4T CMOS wide dynamic range pixels, which we refer as 2T-M and 3T-M configurations, comprising of MOSFETS and memristors. The low leakage currents and low area of memristors helps to achieve the objective of reducing the area, while the possibility to create arrays of memristors and MOSFETs across different layers within the chip, ensure the possibility to scale the circuit architecture.