Polarization-mediated Debye-screening of surface potential fluctuations in dual-channel AlN/GaN high electron mobility transistors

TL;DR

This paper introduces a dual-channel AlN/GaN HEMT design that suppresses surface charge effects using polarization-mediated Debye screening, combining simulation and experimental validation to improve device performance.

Contribution

The study proposes and demonstrates a novel dual-channel architecture with modeling insights that effectively reduce gate lag and surface charge effects in AlN/GaN HEMTs.

Findings

Achieved a gate lag ratio of 0.86 with minimal current collapse.

Validated the design through experimental fabrication and testing.

Provided comprehensive electrostatic and transient modeling results.

Abstract

A dual-channel AlN/GaN/AlN/GaN high electron mobility transistor (HEMT) architecture is proposed, simulated, and demonstrated that suppresses gate lag due to surface-originated trapped charge. Dual two-dimensional electron gas (2DEG) channels are utilized such that the top 2DEG serves as an equipotential that screens potential fluctuations resulting from surface trapped charge. The bottom channel serves as the transistor's modulated channel. Two device modeling approaches have been performed as a means to guide the device design and to elucidate the relationship between the design and performance metrics. The modeling efforts include a self-consistent Poisson-Schrodinger solution for electrostatic simulation as well as hydrodynamic three-dimensional device modeling for three-dimensional electrostatics, steady-state, and transient simulations. Experimental results validated the HEMT design whereby homo-epitaxial growth on free-standing GaN substrates and fabrication of same-wafer dual-channel and recessed-gate AlN/GaN HEMTs have been demonstrated. Notable pulsed-gate performance has been achieved by the fabricated HEMTs through a gate lag ratio of 0.86 with minimal drain current collapse while maintaining high levels of dc and rf performance.