Straintronic magneto-tunneling-junction based ternary content addressable memory

TL;DR

This paper proposes a ternary content addressable memory using straintronic magneto-tunneling junctions, which are energy-efficient but error-prone, to achieve high cell density in non-Boolean computing architectures.

Contribution

It introduces a novel memory architecture combining s-MTJs and transistors, overcoming traditional implementation challenges and enabling high-density ternary memory.

Findings

s-MTJ switches are highly energy-efficient, dissipating only a few attojoules.

The proposed design achieves high cell density compared to traditional implementations.

The architecture is suitable for non-Boolean computing due to error-proneness and low resistance ratio.

Abstract

Straintronic magneto-tunneling junction (s-MTJ) switches, whose resistances are controlled with voltage-generated strain in the magnetostrictive free layer of the MTJ, are extremely energy-efficient switches that would dissipate a few aJ of energy during switching. Unfortunately, they are also relatively error-prone and have low resistance on/off ratio. This suggests that as computing elements, they are best suited for non-Boolean architectures. Here, we propose and analyze a ternary content addressable memory implemented with s-MTJs and some transistors. It overcomes challenges encountered by traditional all-transistor implementations, resulting in exceptionally high cell density.