Parametrization of the radiation induced leakage current increase of NMOS transistors

TL;DR

This paper presents a simple parametrization model for the increase in leakage current of NMOS transistors caused by ionizing radiation, useful for system design and analysis.

Contribution

It introduces a new parametrization method based on transistor transfer characteristics and charge trapping, applicable to both individual transistors and full ASICs.

Findings

The model accurately fits leakage current data from single transistors.

The model successfully predicts supply current increases in ASICs.

The approach aids in designing radiation-hardened systems.

Abstract

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current as a function of the exposure time to ionizing radiation results. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.