Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip

TL;DR

Epiphany-V is a large-scale 1024-core 64-bit RISC System-On-Chip designed in 16nm technology, featuring extensive on-chip memory, mesh networks, and programmable IO, demonstrating advanced chip integration at this scale.

Contribution

This paper presents the design and successful tape-out of a 1024-core RISC processor chip in 16nm technology, showcasing large-scale integration and on-chip communication.

Findings

Successfully manufactured the 1024-core chip.

Demonstrated high integration of cores and on-chip networks.

Achieved functional operation in a complex multi-core system.

Abstract

This paper describes the design of a 1024-core processor chip in 16nm FinFet technology. The chip ("Epiphany-V") contains an array of 1024 64-bit RISC processors, 64MB of on-chip SRAM, three 136-bit wide mesh Networks-On-Chip, and 1024 programmable IO pins. The chip has taped out and is being manufactured by TSMC. This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.