Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology

TL;DR

This paper introduces multi-valued routing tracks for FPGAs in 28nm FDSOI technology, demonstrating significant reductions in energy and area compared to traditional two-valued routing.

Contribution

It presents the design, implementation, and analysis of quaternary and ternary routing tracks in FPGAs using 28nm FDSOI technology, including layout methods and performance comparisons.

Findings

Up to 3x reduction in dynamic switching energy

Up to 2x reduction in routing wire area

10% reduction in routing resource area

Abstract

In this paper we present quaternary and ternary routing tracks for FPGAs, and their implementation in 28nm FDSOI technology. We discuss the transistor level design of multi-valued repeaters, multiplexers and translators, and specific features of FDSOI technology which make it possible. Next we compare the multi-valued routing architectures with equivalent single driver two-valued routing architectures. We show that for long tracks, it is possible to achieve upto 3x reduction in dynamic switching energy, upto 2x reduction in routing wire area and 10% reduction in area dedicated to routing resources. The multi-valued tracks are slightly more susceptible to process variation. We present a layout method for multivalued standard cells and determine the layout overhead.We conclude with various usage scenarios of these tracks.