FPGA Implementation of High Speed Reconfigurable Filter Bank for Multi-standard Wireless Communication Receivers

TL;DR

This paper presents a high-speed FPGA implementation of a reconfigurable filter bank for multi-standard wireless receivers, significantly improving frequency performance and reducing power consumption.

Contribution

It introduces an efficient FPGA-based design of RDFTFB that enhances speed and power efficiency for multi-standard wireless communication applications.

Findings

89.7% increase in maximum operating frequency

18.5% reduction in dynamic power consumption

Effective reconfigurable filter bank implementation on FPGA

Abstract

In next generation wireless communication system, wireless transceivers should be able to handle wideband input signals compromising of multiple communication standards.Such multi-standard wireless communication receivers (MWCRs) need filter bank to extract the desired signal of interest from wideband input spectrum and bring it to the baseband for further signal processing tasks such as spectrum sensing, modulation classification,demodulation etc.In MWCRs,rather any wireless receivers, modulated filter banks, such as Discrete Fourier Transform Filter Banks (DFTFB), are preferred due to their advantages such as lower area, delay and power requirements. To support multi-standard operation, reconfigurable DFTFB (RDFTFB) was proposed by integrating DFTFB with the coefficient decimation method. In this paper, an efficient high speed implementation of RDFTFB on Virtex-7 field programmable gate arrays (FPGA) has been proposed.The proposed approach minimizes the critical path delay between clocked registers thereby leading to significant improvement in the maximum operating frequency of the RDFTFB. Numerically, the proposed implementation leads to 89.7% improvement in the maximum frequency at which RDFTFB can be clocked.Furthermore,proposed implementation leads to 18.5% reduction in the dynamic power consumption.